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VHDL-FPGA-Verilog list
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CORDIC iterative structure of Verilog code
Update : 2025-01-11 Size : 2kb Publisher : zq

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Pipelined structure cordic, can output sin/cos
Update : 2025-01-11 Size : 1kb Publisher : zq

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CORDIC
Update : 2025-01-11 Size : 233kb Publisher : zq

CPLDFPGA embedded application development technology by supporting platinum manual source code, each source has a corresponding note, very useful.
Update : 2025-01-11 Size : 277kb Publisher : mosquito

verilog HDL experimental basis for source code, more practical
Update : 2025-01-11 Size : 983kb Publisher : mosquito

verilog HDL interface test source code, more practical.
Update : 2025-01-11 Size : 1.52mb Publisher : mosquito

Comprehensive Experiment verilog HDL source code, more practical
Update : 2025-01-11 Size : 531kb Publisher : mosquito

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FPGA
Update : 2025-01-11 Size : 107kb Publisher : huang

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Sampling clock procedures: in the baud rate of the sampling clock for the 9600 program-multifrequency program. The baud rate for the 9600 multifrequency program
Update : 2025-01-11 Size : 2kb Publisher : 党小圆

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FPGA using the I2C bus, with LED test function
Update : 2025-01-11 Size : 450kb Publisher : mumu

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Graphics engine using native data structures and fb (Framebuffer) driver
Update : 2025-01-11 Size : 10kb Publisher : forrestyu

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Xilinx ISE9.2 annex for the installation serial number and MAX_II_board_schematics schematics, please download the Friend in need,
Update : 2025-01-11 Size : 235kb Publisher :
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