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VHDL-FPGA-Verilog list
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Used to generate GF (2 ^ m) limited domain constant multiplier Verilog HDL source files of C procedures
Update : 2025-01-11 Size : 168kb Publisher : ChenQiu

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Used to generate GF (2 ^ m) finite field element inversion
Update : 2025-01-11 Size : 169kb Publisher : ChenQiu

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CPLD realize plug memory, and real-time test of good or bad memory. Can be embedded into the system
Update : 2025-01-11 Size : 1kb Publisher : 曾工

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FPGA or CPLD with DAC (DAC0832), the source code is a triangular wave, but also with the simulation, the precision is 8.
Update : 2025-01-11 Size : 53kb Publisher : 刘光钦

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sin generator can produce sin in VHDL of the numerical waveform, and then make the conversion output to dac
Update : 2025-01-11 Size : 1.03mb Publisher : lin

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Subway ticketing system, has multiple functions based on the VHDL
Update : 2025-01-11 Size : 1kb Publisher : lihoukiang

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This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic de
Update : 2025-01-11 Size : 176kb Publisher : panyouyu

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Verilog hdl language used plastic realize DCT algorithm, rational design algorithm is simple and logical development board is red test procedures, worth a visit.
Update : 2025-01-11 Size : 4kb Publisher : panyouyu

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The Verilog design into VHDL design program
Update : 2025-01-11 Size : 324kb Publisher : 黃彥華

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VHDL design will be converted into Verilog design program
Update : 2025-01-11 Size : 17kb Publisher : 黃彥華

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JPEG hardware design using VHDL design source code
Update : 2025-01-11 Size : 282kb Publisher : 黃彥華

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This is a VHDL version of the parser is currently 0.12
Update : 2025-01-11 Size : 13kb Publisher : 黃彥華
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