VHDL-FPGA-Verilog List Page 4138

VHDL-FPGA-Verilog list

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DDRSDRAM Downloaded：0: DDR sdram contains complete source code, simulation of the relevant documents
Update : 2025-01-11 Size : 998kb Publisher : 飞翔
FIFO-DC Downloaded：0: FIFO procedures have been in the Verilog in ModelSim compiler and can be passed through the integrated DC
Update : 2025-01-11 Size : 59kb Publisher : liujl
shipingkonzhi Downloaded：0: Using VHDL realize video control procedures, to achieve image acquisition and compression,
Update : 2025-01-11 Size : 421kb Publisher : 张龙
wishbone2avalone Downloaded：0: By avalen bus adapter i2c bus VHDL program can be applied to Nios Embedded Systems
Update : 2025-01-11 Size : 417kb Publisher : yeyoushi
ddr Downloaded：0: ISE MIG1.6 generated DDR SDRAM controller code (including TESHBENCH)
Update : 2025-01-11 Size : 999kb Publisher : yuling
foudiv Downloaded：0: Can be achieved for any arbitrary waveform at frequency, frequency addition and subtraction through the keys to achieve.
Update : 2025-01-11 Size : 212kb Publisher : 莱密
qiangdaqi(auto) Downloaded：0: Using hardware description language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.
Update : 2025-01-11 Size : 260kb Publisher : 杨操
D0324stimer Downloaded：0: Basketball 24s timer, the components are simple, the function is complicated. Meet the small timing needs.
Update : 2025-01-11 Size : 179kb Publisher : 杨操
ps2_keyboard Downloaded：0: PS2 keyboard to control the content of the experimental procedure is used EDK build a simple system and add custom peripherals (a ps2 keyboard controller) when the keyboard is pressed the corresponding button will scan c
Update : 2025-01-11 Size : 5kb Publisher : 刘安
PN-arraycheck Downloaded：0: QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in seque
Update : 2025-01-11 Size : 377kb Publisher : 戴振华
modelsim6.0 Downloaded：0: ModelSim for use of how to operate and use and installation of how to install
Update : 2025-01-11 Size : 379kb Publisher : kkk
leon3-altera-ep2s60-ddr Downloaded：0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not
Update : 2025-01-11 Size : 112kb Publisher :

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