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VHDL-FPGA-Verilog list
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logic_lock
Downloaded:0
logic lock the VHDL source code, altera platform.
Update
: 2025-01-11
Size
: 2.43mb
Publisher
:
xad
tcl_io
Downloaded:0
Quartus in their own writing tcl, distribution io example.
Update
: 2025-01-11
Size
: 25kb
Publisher
:
xad
io-sortation
Downloaded:0
Quartus senior io distribution, manual example
Update
: 2025-01-11
Size
: 26kb
Publisher
:
xad
bjjfrequent
Downloaded:0
It took me a long time to write the verilogHDL implementation of the precision frequency meter
Update
: 2025-01-11
Size
: 220kb
Publisher
:
小闭
taix_fee
Downloaded:0
verilog HDL prepared Taxi Accounting System
Update
: 2025-01-11
Size
: 541kb
Publisher
:
yukiflower
GuangShanChi
Downloaded:0
Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to
Update
: 2025-01-11
Size
: 678kb
Publisher
:
蔡有才
VH_SYN
Downloaded:0
Standard television signal to generate the synchronization procedures, the use of VHDL and schematic diagram, using Quartus integrated
Update
: 2025-01-11
Size
: 89kb
Publisher
:
蔡有才
FIFO
Downloaded:0
Asynchronous FIFO controller Verilog Design and Implementation
Update
: 2025-01-11
Size
: 5kb
Publisher
:
陈晨
8251Verilog
Downloaded:0
Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
Update
: 2025-01-11
Size
: 15kb
Publisher
:
钟兵
clock
Downloaded:0
fpga clock design, the information is better, for your reference, non-commercial purposes Oh
Update
: 2025-01-11
Size
: 2kb
Publisher
:
max
Verilog
Downloaded:1
The book is a Verilog language design and comprehensive manual that has a great impact on learning the Verilog language and is worth reading.
Update
: 2025-01-11
Size
: 1.64mb
Publisher
:
刘晓琴
lab5_VHDL
Downloaded:0
VHDL source VHDL source VHDL source
Update
: 2025-01-11
Size
: 6kb
Publisher
:
baiyanru
«
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.34
.35
.36
.37
.38
4139
.40
.41
.42
.43
.44
...
4311
»
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