VHDL-FPGA-Verilog List Page 4201

VHDL-FPGA-Verilog list

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EthernetMAC10100Mbps.tar Downloaded：0: ethernet MAC 10,100 M
Update : 2025-01-04 Size : 913kb Publisher : wing
Avalon_VGA Downloaded：0: Avalon_VGA.-- This design provides an interface to the Alca hest VGA daughter card.-- The design comprises of an 8-bit VGA driver with Avalon bus interface s. There are a total of-- three Avalon interface s.
Update : 2025-01-04 Size : 16kb Publisher : 陈朋
xapp616 Downloaded：0: A. Huffman implementation reference desig n in both VHDL and Verilog is provided by the Xili nx
Update : 2025-01-04 Size : 13kb Publisher :
yimazhenque Downloaded：0: 47 decoder for verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Update : 2025-01-04 Size : 21kb Publisher : 刘东辉
lpm_mul Downloaded：0: 8* 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Update : 2025-01-04 Size : 27kb Publisher : 刘东辉
binary2bcd Downloaded：0: This build is for developing a "binary-to- BCD "converter for use in// displaying numeral 's in base-10 so that people can read and interpre not the// numbers more readily than they could if t he numbers were displayed i
Update : 2025-01-04 Size : 41kb Publisher : 陈朋
DaFilter Downloaded：0: /* This program generates the DApkg.vhd fi le that is used to define the DA* filter core and g ives its parameters and the contents of the Dis* tributed Arithmetic Look-up-table "DALUT" ac cording to the DA algorithm
Update : 2025-01-04 Size : 15kb Publisher : 陈朋
DCT_vhdl Downloaded：0: IDCT-M is a medium speed 1D IDCT core-- it ca n accept a continuous stream of 12-bit input word 's at a rate of-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP @ ML MPEG video-- the core is 100 % synthesiza
Update : 2025-01-04 Size : 10kb Publisher : 陈朋
Shifters_vhdl Downloaded：0: -- Title : Barrel Shifter (Pure combinational)-- This VH DL design file is an open design you can redistri bute it and/or-- modify it and/or implement it a fter contacting the author-- You can check the d raft license at
Update : 2025-01-04 Size : 2kb Publisher : 陈朋
cf_interleaver2 Downloaded：0: interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species, a detailed description, is a rare study of the materials a
Update : 2025-01-04 Size : 352kb Publisher : 陈朋
mdct.tar Downloaded：0: This April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete
Update : 2025-01-04 Size : 1.69mb Publisher : 陈朋
fpu_v18 Downloaded：0: fpupack.vhdpre_norm_addsub.vhdaddsub_28.vhdpost_norm_addsub.vhdpre_norm_mul.vhdmul_24.vhdvcom serial_mul.vhdpost_norm_mul.vhdpre_norm_div.vhdserial_div.vhdpost_norm_div.vhdpre_norm_sqrt.vhdsqrt
Update : 2025-01-04 Size : 466kb Publisher : 陈朋

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