VHDL-FPGA-Verilog List Page 4205

VHDL-FPGA-Verilog list

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verilog100 Downloaded：0: a lot of examples and test code, useful for beginners, it is easy to get started
Update : 2025-01-02 Size : 171kb Publisher : bobodu
FPGAUART Downloaded：0: an FPGA-based serial procedures have proven, right Serial do with FPGA reference for a friend and borrow!
Update : 2025-01-02 Size : 304kb Publisher : 舟舟
xc9572_1 Downloaded：0: Xilinx xc9572 cpld achieve servo motor controller, motor control output, Incremental encoder and the reader.
Update : 2025-01-02 Size : 779kb Publisher : 张宏亚
RS_decoder Downloaded：0: rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
Update : 2025-01-02 Size : 15kb Publisher :
I2CSlave Downloaded：0: achieve the Verilog HDL simulation I2C Slave
Update : 2025-01-02 Size : 1kb Publisher : lzy
lru_new Downloaded：0: using LRU replacement algorithm. This algorithm to choose the most long visit is not being replaced as a block by block. To achieve LRU algorithm, in block form for each one to set up a Counter (cnt0, cnt1. cnt2, cnt3,).
Update : 2025-01-02 Size : 1kb Publisher : wangjiao
ls12_mux16 Downloaded：0: A 16-bit multiplier veriolog language. Use a novice.
Update : 2025-01-02 Size : 959kb Publisher : 1412
I2C_1.1 Downloaded：0: Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo's---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later
Update : 2025-01-02 Size : 3kb Publisher : 郑开科
tst_ds1621 Downloaded：0: -- State machine for reading data from Dall as 1621---- Testsystem for i2c controller
Update : 2025-01-02 Size : 2kb Publisher : 郑开科
wishbone_i2c_master Downloaded：0: -- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman
Update : 2025-01-02 Size : 5kb Publisher : 郑开科
add_sub_lab2 Downloaded：0: experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.
Update : 2025-01-02 Size : 59kb Publisher : 徐轶尊
110detector_lab Downloaded：0: a simple survey of 110 three detectors, and a logical map vhdl description, including reports and experimental test plan.
Update : 2025-01-02 Size : 140kb Publisher : 徐轶尊

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