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VHDL-FPGA-Verilog list
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1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input/output, with DMA function, the ip xilinx
Update : 2025-01-04 Size : 615kb Publisher : 刘超

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TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!
Update : 2025-01-04 Size : 19kb Publisher : 刘超

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5 pm code and explanations verilog code Almost all the interviews will IC asked this question, summed up in the ranks about fat, learn together!
Update : 2025-01-04 Size : 1kb Publisher : 刘超

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This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
Update : 2025-01-04 Size : 2.7mb Publisher : 李伟

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This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
Update : 2025-01-04 Size : 332kb Publisher : 李伟

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bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
Update : 2025-01-04 Size : 59kb Publisher : 王琪

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the booth algorithm to implement the 32bit 's multiplication.
Update : 2025-01-04 Size : 55kb Publisher : 王琪

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lot of verilog example, just beginners more useful
Update : 2025-01-04 Size : 111kb Publisher : kg

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verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
Update : 2025-01-04 Size : 609kb Publisher : 沈佳麒

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verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... and test module used to verify the state is working
Update : 2025-01-04 Size : 6kb Publisher : 陆磊

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VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
Update : 2025-01-04 Size : 285kb Publisher : 计算机

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Wishbone dma ip core
Update : 2025-01-04 Size : 7kb Publisher : liwen
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