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VHDL-FPGA-Verilog list
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e12HDB3
Downloaded:0
Electronic Engineering, Tsinghua University HDB3 lab report include: M sequence generator, encoders, decoders
Update
: 2025-01-20
Size
: 5.66mb
Publisher
:
夏冬
ug871_vivad_HLS_tutorial
Downloaded:0
Vivado HLS Xilinx high level integrated tool for the use of software instructions
Update
: 2025-01-20
Size
: 7.41mb
Publisher
:
taxue4485
clk_generator
Downloaded:0
Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
Update
: 2025-01-20
Size
: 381kb
Publisher
:
duzengquan
absolute2relative_coding
Downloaded:0
DPSK code conversion relative and absolute code
Update
: 2025-01-20
Size
: 2.13mb
Publisher
:
sxx
squa
Downloaded:0
ISE Verilog language implementations under wave generator
Update
: 2025-01-20
Size
: 3.07mb
Publisher
:
sxx
counter6display
Downloaded:0
ISE Verilog environment becomes realized under six counter with 7-segment display CRT
Update
: 2025-01-20
Size
: 175kb
Publisher
:
sxx
coubter_key
Downloaded:0
ISE Verilog programming environment under mechanical debounces
Update
: 2025-01-20
Size
: 431kb
Publisher
:
sxx
cnt63dis
Downloaded:0
ISE Verilog programming environment under 63 binary counter with 7 segment decoder CRT display
Update
: 2025-01-20
Size
: 1.19mb
Publisher
:
sxx
addafilter
Downloaded:0
digital filter based on Nios2
Update
: 2025-01-20
Size
: 26.84mb
Publisher
:
胡哲哲
digitron
Downloaded:0
Digital display, which contains the source code and many other top level schematics decoder circuit and finally a combination.
Update
: 2025-01-20
Size
: 460kb
Publisher
:
木子
digitron
Downloaded:0
Digital display, which contains the source code and many other top level schematics decoder circuit and finally a combination.
Update
: 2025-01-20
Size
: 207kb
Publisher
:
木子
VGA3
Downloaded:0
ISE verilog
Update
: 2025-01-20
Size
: 810kb
Publisher
:
cwx
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