VHDL-FPGA-Verilog List Page 456

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .51 .52 .53 .54 .55 456.57 .58 .59 .60 .61 ... 4311 »

lab06 Downloaded：0: Design of a 4* 4bit register file includes a read port and a write port data can be read 0 to No. 3 port by reading any address read and write data can be written to 0 to No. 3 by writing to any address port port is &quo
Update : 2025-01-20 Size : 279kb Publisher : 李元月
ISE Downloaded：0: Design a four comparators, drawing out level circuit diagram, complete the design using verilog language.
Update : 2025-01-20 Size : 233kb Publisher : 李元月
demo11 Downloaded：0: Implementing a 8bit counter is reset when the count value 8' hF0 reset the counter for accumulator operation, in steps of 1, after the count reaches 8' hFF, resumes counting 0 about every 0.5 seconds count is incre
Update : 2025-01-20 Size : 294kb Publisher : 李元月
16FFT Downloaded：0: The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary comp
Update : 2025-01-20 Size : 722kb Publisher : 我是谁
1024FFT Downloaded：0: The xFFT1024 fast Fourier transform (FFT) Core computes a 1024-point complex FFT. The input data is a vector of 1024 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginar
Update : 2025-01-20 Size : 684kb Publisher : 我是谁
CRC Downloaded：0: The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the mo
Update : 2025-01-20 Size : 206kb Publisher : 我是谁
i2cBUS Downloaded：0: The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source files
Update : 2025-01-20 Size : 2.15mb Publisher : 我是谁
IO Downloaded：0: NEXYS4 and ISE14.7 developed parallel IO interface based, to the digital display digital scroll function
Update : 2025-01-20 Size : 107kb Publisher : 叶爽
e1 Downloaded：0: Tsinghua University, Department of Electronics, combinational logic experimental design includes multiplexer, decoder design, four adder design
Update : 2025-01-20 Size : 6.19mb Publisher : 夏冬
s5 Downloaded：0: Tsinghua University, Department of Electronics, sequential logic test report include: trigger design, counter design, accumulator design, the sequence detector design/finite state machine
Update : 2025-01-20 Size : 4.56mb Publisher : 夏冬
e8 Downloaded：0: Tsinghua University, Department of Electronics, digital clock design lab report (Article 8 experiments)
Update : 2025-01-20 Size : 3.32mb Publisher : 夏冬
e10 Downloaded：0: Electronic Engineering, Tsinghua University, frame synchronizer design experiments starting status report as loss of gait, by a frame synchronization code to determine the correctness of the frame. Judgment is correct, t
Update : 2025-01-20 Size : 2.46mb Publisher : 夏冬

« 1 2 ... .51 .52 .53 .54 .55 456.57 .58 .59 .60 .61 ... 4311 »

Search in result