VHDL-FPGA-Verilog List Page 461

VHDL-FPGA-Verilog list

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Tetris-VHDL Downloaded：0: Using FPGA and VGA monitor to develop a Tetris game. Developed using VHDL language and Xilinx .
Update : 2025-01-20 Size : 3.79mb Publisher : 彭铭仕
xulie Downloaded：0: Sequence detection, after detecting a sequence of 11010 lighting, files are written with verilog
Update : 2025-01-20 Size : 344kb Publisher : 夏冬青
spi_verilog Downloaded：0: In more details: 1. The master pulls SSEL down to indicate to the slave that communication is starting (SSEL is active low). 2. The master toggles the clock eight times and sends eight data bits on its MOSI line. At the
Update : 2025-01-20 Size : 8kb Publisher : michael
CNT4 Downloaded：0: Quaternary adding counter
Update : 2025-01-20 Size : 165kb Publisher : 曾
Buffer Downloaded：0: parametrizable register and mux in VHDL of data rage, using std_logic_vector type
Update : 2025-01-20 Size : 2kb Publisher : Felipe
wgsph_lab Downloaded：0: DDFS Verilog DDFS Verilog DDFS Verilog DDFS Verilog
Update : 2025-01-20 Size : 1kb Publisher : Mohit
ETH_SRC Downloaded：0: ethernet Verilog
Update : 2025-01-20 Size : 1.2mb Publisher : 王长友
LVDS_SRC Downloaded：0: lvds Verilog 512 frame
Update : 2025-01-20 Size : 434kb Publisher : 王长友
uart_control Downloaded：0: uart contrl Verilog
Update : 2025-01-20 Size : 1kb Publisher : 王长友
rxd_interface Downloaded：0: Verilog uart rxdinterface
Update : 2025-01-20 Size : 1kb Publisher : 王长友
txd_control Downloaded：0: uart TXD——contrl Verilog
Update : 2025-01-20 Size : 1kb Publisher : 王长友
rxd_control Downloaded：0: uart rxd contrl Verilog
Update : 2025-01-20 Size : 1kb Publisher : 王长友

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