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VHDL-FPGA-Verilog list
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decimal divider
Update : 2025-01-20 Size : 336kb Publisher : hp

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phase discriminator
Update : 2025-01-20 Size : 295kb Publisher : hp

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seven-segment encoder
Update : 2025-01-20 Size : 263kb Publisher : hp

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counter encoder
Update : 2025-01-20 Size : 353kb Publisher : hp

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fpga s fsmc communication codes
Update : 2025-01-20 Size : 9.41mb Publisher : 林坤城

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Cache Verilog HDL implementation. (Including directly linked and set associative)
Update : 2025-01-20 Size : 6kb Publisher : Lei

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RS485 driver for FPGA
Update : 2025-01-20 Size : 16.43mb Publisher : Jeff_yin

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segled display dynamicly controled by FPGA
Update : 2025-01-20 Size : 4.96mb Publisher : Jeff_yin

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driver for DC moto controled by FPGA
Update : 2025-01-20 Size : 111kb Publisher : Jeff_yin

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3c10 step move moto controled by FPGA program write by verilog
Update : 2025-01-20 Size : 234kb Publisher : Jeff_yin

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driver program for AD6645 on FPGA,and translated by UART
Update : 2025-01-20 Size : 5.2mb Publisher : Jeff_yin

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This code has SPWM generation with 8 bit feedback.with the help of feedback can adjust the amplitude of sine wave.
Update : 2025-01-20 Size : 1kb Publisher : Motasim Masood
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