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VHDL-FPGA-Verilog list
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This code is for led blinking in vhdl for fpga compiled in altera Quartus 13.
Update : 2025-01-20 Size : 233kb Publisher : Motasim Masood

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THis code is for Spwm based inverter.with 25khz carrier frequency of pwm and 60 hz frequency which is modulated on pwm.compiled in altera Quartus
Update : 2025-01-20 Size : 1.51mb Publisher : Motasim Masood

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Improved Verilog implementation of 32 bit ahead carry adder
Update : 2025-01-20 Size : 4kb Publisher : 李某人

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FPGA_NIOSII U-disk storage, U disk can read and write files to a project
Update : 2025-01-20 Size : 12.82mb Publisher : 何学强

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4 bit full adder based on DE1
Update : 2025-01-20 Size : 214kb Publisher : 陈云成

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This is a description of FSM code is part of my project project hope for everyone to share, too, and common progre
Update : 2025-01-20 Size : 26kb Publisher : susanyang

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vga for fpga vhdl so enjoy learn about vhdl
Update : 2025-01-20 Size : 1kb Publisher : hicham hajoui

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the ball in fpga fixe or move it s the same enjoy it it
Update : 2025-01-20 Size : 35kb Publisher : hicham hajoui

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CPLD key consumer shake control, digital tube display. Debug through. Can be used directly
Update : 2025-01-20 Size : 289kb Publisher : 将成

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Use and set & method common shift register to write VHDL models. Under clock control the input data registers, the output data in the output condition is satisfied.
Update : 2025-01-20 Size : 833kb Publisher : 陈睿祺

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Mealy-type single-process data monitoring. Achieve 100,101 data monitoring, enabling multiple portfolio monitoring, change transplantation convenient and simple.
Update : 2025-01-20 Size : 474kb Publisher : 陈睿祺

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This file is the VHDL code for controlling the stepping motor. The clock driving the stepping motor driver module. through signal it can control the direction of the stepping motor.
Update : 2025-01-20 Size : 292kb Publisher : parksehun
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