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VHDL-FPGA-Verilog list
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Using Verilog HDL language of the two frequency, output frequency is half the input frequency.
Update : 2025-01-20 Size : 32kb Publisher : 李建文

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This document is based on xilinx ise platform counter, adjustable pulse generation, but also for the division.
Update : 2025-01-20 Size : 209kb Publisher :

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This file uses the FPGA analog DIP switches, when the DIP switch is set to 0 or 1, led lights lit correspondence
Update : 2025-01-20 Size : 830kb Publisher :

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SPI interface protocol, the spi bus converted into LOCAL BUS bus
Update : 2025-01-20 Size : 2kb Publisher : jf.chen

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Project whitch implement picoblaze MCU and uart communication.
Update : 2025-01-20 Size : 520kb Publisher : Jaroslav

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this about embedded system
Update : 2025-01-20 Size : 11.19mb Publisher : Velda Talitha

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REVESIBLE DATA HIDING
Update : 2025-01-20 Size : 5.49mb Publisher : madhuri

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Quartus under the environment of a serial procedures written in Verilog, RTL and timing simulation has be passed
Update : 2025-01-20 Size : 583kb Publisher : 王昕然

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One hundred binary counter, decimal counter increased ten count as a template, you can write a number of analog counter. Ninety-nine cleared.
Update : 2025-01-20 Size : 545kb Publisher : 陈睿祺

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EP3C5E144 type FPGA to send 429 signal, through the 429 board received verification
Update : 2025-01-20 Size : 4.5mb Publisher : 毛云峰

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Through the serial port to send the command to control the FPGA send 429 signal, and through the verification of the board.
Update : 2025-01-20 Size : 1.18mb Publisher : 毛云峰

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Through the serial port to send the command to send the FPGA to receive the 429 card board to send the signal, and light up the corresponding LED.
Update : 2025-01-20 Size : 1.53mb Publisher : 毛云峰
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