VHDL-FPGA-Verilog List Page 470

VHDL-FPGA-Verilog list

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ddr2_controller Downloaded：0: A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
Update : 2025-01-20 Size : 90kb Publisher : inru
scope-firmware Downloaded：0: Open-source Spartan-6 compatible project that implements a USB digital scope firmware by alown, including tests.
Update : 2025-01-20 Size : 314kb Publisher : inru
debouncer_vhdl Downloaded：0: RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
Update : 2025-01-20 Size : 69kb Publisher : inru
wu4g Downloaded：0: Wake up network layer for a Hardware based radio project, written in VHDL.
Update : 2025-01-20 Size : 213kb Publisher : inru
USRP-PID-Controller-clean Downloaded：0: PID feedback controller project for USRP1 boards (FPGA with a convenient analog front manufactured by ettus research). Implements a bitstream as well as python-based user interface.
Update : 2025-01-20 Size : 993kb Publisher : inru
tmds_decoder Downloaded：0: Tryout HDMI decoder for Xilinx-based boards, using SERDES logic. Different implementations.
Update : 2025-01-20 Size : 49kb Publisher : inru
s6iserdes-master Downloaded：0: ISERDES implementation and example code for Xilinx-based boards, e.g. Spartan 6.
Update : 2025-01-20 Size : 52kb Publisher : inru
FangDou Downloaded：0: Verilog language used mechanical buttons stabilization program, use ISE10.0 version.
Update : 2025-01-20 Size : 62kb Publisher : zhangbiao
FangDou_reg Downloaded：0: Verilog language using mechanical keys stabilization program, the method of using a shift register eliminate shaking.
Update : 2025-01-20 Size : 254kb Publisher : zhangbiao
mileage Downloaded：0: I use the FPGA to achieve。 It is used to calculate the distance, can be used in the taxi meter, to achieve the mileage of the count。
Update : 2025-01-20 Size : 2.71mb Publisher : 宋冀生
time Downloaded：0: I use the FPGA to achieve, for the calculation of time, can be used in a taxi meter, to achieve the time count.
Update : 2025-01-20 Size : 274kb Publisher : 宋冀生
Divider_Verilog_ISE Downloaded：0: Using Verilog language division procedures, including odd division, even dividing and many other routines.
Update : 2025-01-20 Size : 325kb Publisher : zhangbiao

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