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VHDL-FPGA-Verilog list
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Binary tree in system verilog using classes, and automatic function
Update : 2025-01-20 Size : 1kb Publisher : Sam

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Spread-Spectrum-Analyzer in verilog with testbench
Update : 2025-01-20 Size : 477kb Publisher : Sam

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Sequence Detector
Update : 2025-01-20 Size : 3.33mb Publisher : xxl

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a 32bit non-restoring square root with CSM in VHDL
Update : 2025-01-20 Size : 3kb Publisher : ali

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SHA3 VHDL implementation FPGA proven
Update : 2025-01-20 Size : 202kb Publisher : Zero

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pipelined fft/ifft 256 point ip core
Update : 2025-01-20 Size : 217kb Publisher : SANDEEP

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Fpga controlled by a band-da made a sinusoidal signal, written in vhdl, with nco
Update : 2025-01-20 Size : 1.3mb Publisher : 任天鹏

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Fpga based fft transform, use ip core implementation. Written in vhdl
Update : 2025-01-20 Size : 4.23mb Publisher : 任天鹏

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Ip core implementation using fft. Written in vhdl
Update : 2025-01-20 Size : 5.25mb Publisher : 任天鹏

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With fpga control ad acquisition, with vhdl written to control the sampling rate
Update : 2025-01-20 Size : 3.86mb Publisher : 任天鹏

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Traffic lights, verilog, VHDL, modelsim
Update : 2025-01-20 Size : 1kb Publisher : 金小泼

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Display a signal, the resolution information can be seen as 1280 x 720 @ 60P, the display shows the standard 8-color vertical color bar
Update : 2025-01-20 Size : 80kb Publisher : 张少伟
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