VHDL-FPGA-Verilog List Page 477

VHDL-FPGA-Verilog list

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4bitmultiplier Downloaded：0: its a verilog coding of a multiplier. it multiply 2 values each of width having 4bit
Update : 2025-01-20 Size : 1kb Publisher : nizam42
Sequence-Detector Downloaded：0: The use of a state machine sequence detector for detecting " 1101." With btn [1] and btn [0] as input representing 1 and 0, the current digital input digital tube display in the last one, whenever entering a new
Update : 2025-01-20 Size : 4kb Publisher : 刘东辉
Digital-Password-Lock Downloaded：0: Digital lock specific requirements are as follows: 1. The system password is set using DIP switches sw [7: 0], is limited to four passwords sw [7: 6], sw [5: 4], sw [3: 2], sw [1: 0], respectively left to right 1,2,3,4 d
Update : 2025-01-20 Size : 5kb Publisher : 刘东辉
DPLL Downloaded：0: The input signal to achieve the 1.5 multiplier, input digital signal frequency range is 1050 ~ 1100Hz (not necessarily a 50 duty cycle square wave, and the input signal frequency may change slowly in 1050 ~ 1100Hz, frequ
Update : 2025-01-20 Size : 4kb Publisher : 刘东辉
Screen-saver Downloaded：0: Design a screen saver, its compilation, simulation, download. Screen Savers specific requirements are as follows: 1. Use the attached ISE CORE Generator block RAM/ROM data stored in an image, this module as part of a scr
Update : 2025-01-20 Size : 5kb Publisher : 刘东辉
Synchronous-FIFO Downloaded：0: FIFO is an abbreviation of the English FIRST-IN-FIRST-OUT, which is a FIFO data buffer, it is the difference between ordinary memory is no external write address lines, so very convenient to use, but the drawback is that
Update : 2025-01-20 Size : 4kb Publisher : 刘东辉
Four-bit-signed-number-division Downloaded：0: Design of four sentinel signed integer divider (op = aibi), the software downloaded to the FPGA board through simulation to validate [the specific requirements] 1, using the clock as an input clock signal having a freque
Update : 2025-01-20 Size : 4kb Publisher : 刘东辉
Spring_2010 Downloaded：0: WeiKun Open Sourse Handheld Oscilloscope Spring 2010
Update : 2025-01-20 Size : 1.66mb Publisher : Elante
Winter_2010 Downloaded：0: WeiKun Open Sourse Handheld Oscilloscope winter 2010
Update : 2025-01-20 Size : 2.02mb Publisher : Elante
Spring_2011 Downloaded：0: WeiKun Open Sourse Handheld Oscilloscope Spring 2011
Update : 2025-01-20 Size : 2.85mb Publisher : Elante
The-first-edition-oscilloscope Downloaded：0: The first edition open sourse handheld oscilloscope
Update : 2025-01-20 Size : 248kb Publisher : Elante
uart Downloaded：0: Atmega 328 UART clone with testbench, cannot be synthesized to gates
Update : 2025-01-20 Size : 64kb Publisher : Sam

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