VHDL-FPGA-Verilog List Page 507

VHDL-FPGA-Verilog list

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code Downloaded：0: Dynamic scan keyboard, and then the key results are displayed on the LCD, the use of the shake function
Update : 2025-01-21 Size : 1kb Publisher : 李娜
code Downloaded：0: Classical circuit design (HUAWEI) and the design of the circuit constraint file (HUAWEI)
Update : 2025-01-21 Size : 360kb Publisher : 李娜
saopin_saveV2 Downloaded：0: Use DDS principle in the FPGA to achieve the sweep function and use of high-speed data acquisition AD, while the completion of the digital peak detection, and with high-speed data output DA
Update : 2025-01-21 Size : 11.95mb Publisher : 刘军
ADS8509 Downloaded：0: FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing
Update : 2025-01-21 Size : 1.91mb Publisher : 刘军
DAC902_model Downloaded：0: Written in verilog 12 parallel DAC902 module.Can be run on the FPGA
Update : 2025-01-21 Size : 103kb Publisher : 吴添杨
segled Downloaded：0: Digital fpga Verilog HDL Code
Update : 2025-01-21 Size : 433kb Publisher : 林坤城
sdram Downloaded：0: xilinx sdram
Update : 2025-01-21 Size : 506kb Publisher : 姜明明
sdram_5 Downloaded：0: SDRAM is verilog description, including top-level design, testbench code, an accurate description of
Update : 2025-01-21 Size : 6kb Publisher : micheal zhang
nfc Downloaded：0: Verilog description of near field communication, including the vector name is defined, an accurate description of the top-level design, etc.
Update : 2025-01-21 Size : 2kb Publisher : micheal zhang
ram_3 Downloaded：0: RAM in verilog description, including vector name is defined, an accurate description of the top-level design, etc.
Update : 2025-01-21 Size : 1kb Publisher : micheal zhang
usb_host_device Downloaded：0: usb clock verilog description, including the vector name is defined, an accurate description of the top-level design, etc.
Update : 2025-01-21 Size : 144kb Publisher : micheal zhang
pci Downloaded：0: usb clock verilog description, including the vector name is defined, an accurate description of the top-level design, etc.
Update : 2025-01-21 Size : 202kb Publisher : micheal zhang

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