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VHDL-FPGA-Verilog list
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The basic two pairs 4 decoder, easy to work more than four 7-segment LED scanning control
Update : 2025-01-21 Size : 1.3mb Publisher : chen y y

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The decoder then extended to 2x4 3x8 decoder can control eight LED driving scanning circuit
Update : 2025-01-21 Size : 1.21mb Publisher : chen y y

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Basic 7-segment LED, decoding circuit can also change the associated output control codes corresponding to the associated display
Update : 2025-01-21 Size : 1.24mb Publisher : chen y y

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A combination of eight key anti-bounce, plus latch circuit allows the switching action is more stable
Update : 2025-01-21 Size : 3.01mb Publisher : chen y y

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Simulation of DDS chip based on FPGA. Can produce more than 10M sine wave. And the waveform is not distorted.
Update : 2025-01-21 Size : 21kb Publisher : dalizi

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Produced by the FPGA PWM wave frequency and duty cycle can be adjusted to achieve convenient transplant.
Update : 2025-01-21 Size : 114kb Publisher : 小松

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Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface (SMI) to transfer management data between an Ethernet Medi
Update : 2025-01-21 Size : 5kb Publisher : sherry

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encode and decode hdb3 using verilog HDL
Update : 2025-01-21 Size : 565kb Publisher : 杨洪吉

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Implementation of Sine wave output with different phase.
Update : 2025-01-21 Size : 4.04mb Publisher : 俞少迪

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convert 4 bit data to 8 bit data
Update : 2025-01-21 Size : 2kb Publisher : 李娜

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A, B two serial data is converted to parallel data, and then enter the adder module, add the output.
Update : 2025-01-21 Size : 4kb Publisher : 李娜

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7 bit voting machine, realize the voting choice results present the encoding.
Update : 2025-01-21 Size : 1kb Publisher : 李娜
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