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VHDL-FPGA-Verilog list
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Sequence detector using a shift register implementation, detection of a specific sequence 101011
Update : 2025-01-22 Size : 1kb Publisher : 赵健

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Synchronous adding counters, D flip-flop implemented using binary counter
Update : 2025-01-22 Size : 1kb Publisher : 赵健

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xilinx vhdl code for random number generator and prime number check. it can be used for cryptography
Update : 2025-01-22 Size : 5.75mb Publisher : chandrapal singh

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Asynchronous adding counter using D flip-flop to achieve binary counter
Update : 2025-01-22 Size : 1kb Publisher : 赵健

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Verilog language to achieve water lights on the FPGA.
Update : 2025-01-22 Size : 973kb Publisher : 陈图桓

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Finit state machine proce
Update : 2025-01-22 Size : 265kb Publisher : Sat

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verilog vivado xilinx
Update : 2025-01-22 Size : 666kb Publisher : Cht

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process m sequence with 2Ask includes frequency divider, m sequence generator, sine signal generator and MUX
Update : 2025-01-22 Size : 1.14mb Publisher : changquan

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pipeline with MIPS implementation, using verilog. Resolve conflicts pipeline.
Update : 2025-01-22 Size : 4.79mb Publisher : 勿苛刻

verification of AD9129-EVB based on FPGA
Update : 2025-01-22 Size : 24kb Publisher : 木子

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Seven-segment LED driver, the DE2 board to enter numbers by toggle switch in the digital tube display
Update : 2025-01-22 Size : 280kb Publisher : 李西平

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Stepper motor drive, using Verilog language crossover method designed to achieve has been rotated.
Update : 2025-01-22 Size : 430kb Publisher : 李西平
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