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VHDL-FPGA-Verilog list
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a iic_100k program using a verilog HDL
Update : 2025-01-22 Size : 2kb Publisher : 谷雨

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a learning diary about TimeQuest analyse
Update : 2025-01-22 Size : 1.13mb Publisher : 谷雨

fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
Update : 2025-01-22 Size : 3kb Publisher : 谷雨

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pipeline_lut_multiplier ,a multiplier based on look up tablets ,and it is programing in verilog language
Update : 2025-01-22 Size : 5kb Publisher : 谷雨

pipeline_streamlined_divider, a divider using pipeline technology in verilog HDL language
Update : 2025-01-22 Size : 3kb Publisher : 谷雨

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FIFO FSM Implementation
Update : 2025-01-22 Size : 1kb Publisher : mt

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this file is a driver for rs-232 protocol. tx and rx. working for as uart protocol
Update : 2025-01-22 Size : 2kb Publisher : mohsen

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this is a code for a sorter block. read data a RAM and sort them. then write data in RAM
Update : 2025-01-22 Size : 5kb Publisher : mohsen

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Arithmetic and Logic Unit
Update : 2025-01-22 Size : 62kb Publisher : Sandeep

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blocking and non blocking statement in verilog example.
Update : 2025-01-22 Size : 57kb Publisher : Sandeep

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Frequency meter, for an unknown frequency of the periodic signal frequency measurement, in 1s signal cycle counts, to obtain the frequency of the periodic signal.
Update : 2025-01-22 Size : 3kb Publisher : 赵健

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Sequence detector, finite state machine, detection of a specific sequence 101011
Update : 2025-01-22 Size : 1kb Publisher : 赵健
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