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VHDL-FPGA-Verilog list
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To achieve the dynamic LED dot matrix Chinese characters display design, by modifying the ROM module to change the display of Chinese characters
Update : 2025-01-23 Size : 536kb Publisher : tom

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VHDL design with a 6-bit binary counter
Update : 2025-01-23 Size : 1kb Publisher : 莫灵敏

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Based Verilog language TLC549 drive, drive digital control
Update : 2025-01-23 Size : 1.8mb Publisher : 林安

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这个设计范例使用 DE2-115 上的 VGA 输出、音频编解码芯片以及 TV 解码芯片( U6)播放 来自 DVD 播放器输出的视频和音频信号。 图 6-1 给出了设计的原理框图。系统主要由两个 模块组成,它们是 I2C_AV_Config 以及 TV_to_VGA 模块。 TV_to_VGA 模块由 ITU-R 656 解 码器, SDRAM 帧缓冲器, YUV422 转 YUV444, YcrCb 转 RGB 以及 VGA 控制器
Update : 2025-01-23 Size : 13.26mb Publisher : gxhgxhgxh

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DE2-115 出厂时写有默认的配置数据,用于演示开发板的一些基本特征。下面给出了默认配 置的存放位置,和执行默认配置需要准备的工作。
Update : 2025-01-23 Size : 16.59mb Publisher : gxhgxhgxh

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FPGA 1602
Update : 2025-01-23 Size : 4.25mb Publisher : 李海裴

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FPGA clock
Update : 2025-01-23 Size : 1.98mb Publisher : 李海裴

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FPGA realization LCD12864 drive (embedded function generator required state machine), parallel data transmission, VHDL implementation.
Update : 2025-01-23 Size : 13.5mb Publisher : WSong

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DDS on FPGA (VHDL), only FM, AM can be implemented in an external DA. (With triangular wave, sine wave, square wave rom call)
Update : 2025-01-23 Size : 534kb Publisher : WSong

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FPGA implementation using UDP/IP protocol to transfer
Update : 2025-01-23 Size : 18.84mb Publisher : 朱诗迪

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A single cycle CPU
Update : 2025-01-23 Size : 1.52mb Publisher : 乔嘉林

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Hello everyone, I am a graduate student at Fudan University. This resource is based on VHDL language of M bit by bit N divider. Where M/N, quotient M bits, the remainder is N bits. In Moim design verification and validat
Update : 2025-01-23 Size : 2kb Publisher : ljt
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