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VHDL-FPGA-Verilog list
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NC divider design. It includes an even divide, and odd division.
Update : 2025-01-23 Size : 314kb Publisher : 谢英才

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Based on Verilog AD9910 procedure, realization of QPSK modulation, just add a small amount of code can achieve 8PSK modulation
Update : 2025-01-23 Size : 5kb Publisher :

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The use of open power system protection device in a program, only need to modify the address can be used with DSP together.
Update : 2025-01-23 Size : 152kb Publisher : wangfei

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Flashing lights, digital tube counting 1000, for beginners to learn
Update : 2025-01-23 Size : 673kb Publisher : 陈元

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Ethernet drive-by Verilog language can achieve up to eight Ethernet, plus after PHY, can achieve a ping
Update : 2025-01-23 Size : 5.73mb Publisher : 罗军

This procedure is a host-based communications program light of CPLD95288 Xilinx chip development, AD7656AD capture capability.
Update : 2025-01-23 Size : 3kb Publisher : 杜含宇

This procedure is based on Xilinx s CPLD95288 light communication chip development, AD7656AD acquisition the program.
Update : 2025-01-23 Size : 2kb Publisher : 杜含宇

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All digital phase-locked loop based on VHDL write program this program can complete the relevant function
Update : 2025-01-23 Size : 374kb Publisher : 赵政桐

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FIR filter source code and instantiated figure and waveform simulation diagram
Update : 2025-01-23 Size : 378kb Publisher : 孙旭丽

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cordic algorithm project.
Update : 2025-01-23 Size : 229kb Publisher : cuong

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32-bit accumulator, including 32-bit adder and register, procedures and simulation files included, can be run directly under the corresponding environment
Update : 2025-01-23 Size : 194kb Publisher : chaoshui

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Waveform memory design using VHDL file can load some of the waveform data files contain simulation can be run directly Figure
Update : 2025-01-23 Size : 336kb Publisher : chaoshui
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