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VHDL-FPGA-Verilog list
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AGC (automatic gain control) can refer to the Verilog code design
Update : 2025-01-23 Size : 2kb Publisher : ying

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Display image via VGA port in FPGA bord
Update : 2025-01-23 Size : 3.28mb Publisher : karim

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Interleaving with error correction
Update : 2025-01-23 Size : 314kb Publisher : karim

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VHDL Implementation Interleaver
Update : 2025-01-23 Size : 552kb Publisher : karim

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the program for vivado study on SOC
Update : 2025-01-23 Size : 20kb Publisher : fishman

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FPGA uart
Update : 2025-01-23 Size : 486kb Publisher : 郭晓旭

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fpga example
Update : 2025-01-23 Size : 1.22mb Publisher : 郭晓旭

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2-div frequency using D flip-flop circuit.
Update : 2025-01-23 Size : 1kb Publisher : lu

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Complete self-plus-function LED, which contains complete instructions and test files
Update : 2025-01-23 Size : 3.07mb Publisher : 蔡润泽

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The main driver to achieve AD conversion module, including AD test modules
Update : 2025-01-23 Size : 3.24mb Publisher : 蔡润泽

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This module is to achieve the conversion of Gray code and binary code, and give the simulation test file
Update : 2025-01-23 Size : 2.92mb Publisher : 蔡润泽

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RTL grade of Verilog codes for reducing antenna effect
Update : 2025-01-23 Size : 17kb Publisher : 曹晨曦
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