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VHDL-FPGA-Verilog list
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Initializes Toppoly TD043MTEA1 LCD. R02: Type 1 Dot inversion, VD and HD low polarity, Latch data on falling edge, 800x480RGB R03: Software register standby, pre-charge enabled, 100 drive capacity, PWM enabled, VGL pump
Update : 2025-01-23 Size : 1kb Publisher : Candace

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Introduced the use of qsys, is a version of the quartus13.0 based operation, a good tutorial
Update : 2025-01-23 Size : 4.95mb Publisher : 海风

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This program implements functionality GPS receiver for receiving the time information, and encoding IRIG-B time code is formed, while with the device 485 to communicate via the bus. Including schematics, SCM and CPLD pro
Update : 2025-01-23 Size : 454kb Publisher : jiawenjing

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DDS-based signal generator
Update : 2025-01-23 Size : 684kb Publisher :

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Sdram page can read and write capabilities, including the addition of two FIFO buffers, just a little change can join the project.
Update : 2025-01-23 Size : 4kb Publisher :

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verilog write, use fpga comes tlc549 ADC chip voltage signal real-time acquisition and through digital display.
Update : 2025-01-23 Size : 2kb Publisher :

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Receive a small amount of a continuous string of verilog implementation, added FIFO module, can be used under slightly modified.
Update : 2025-01-23 Size : 2kb Publisher :

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Use sdram verilog-driven single-byte read and write, you can learn the most basic functions sdram, sdram reference learning program.
Update : 2025-01-23 Size : 3kb Publisher :

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verilog written, cleverly accomplished by counting the triangular waveform can be output directly to da.
Update : 2025-01-23 Size : 126kb Publisher : 李俊

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verilog write, use the dds fpga way, you can output an arbitrary waveform signal occurs.
Update : 2025-01-23 Size : 495kb Publisher : 李俊

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Used to test series 10010 program, Verilog state machine practice
Update : 2025-01-23 Size : 373kb Publisher : 王佳

此程序为用Verilog编写的可实现中值滤波,sobel边沿检测,腐蚀膨胀运算,算法强大。
Update : 2015-04-20 Size : 512.42kb Publisher : mazhonglei_468@163.com
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