VHDL-FPGA-Verilog List Page 568

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .63 .64 .65 .66 .67 568.69 .70 .71 .72 .73 ... 4311 »

FFT16 Downloaded：0: FFT transform code, suitable for beginners to learn. 16 FFT
Update : 2025-01-23 Size : 2kb Publisher : 吕攀攀
Infrared-light-transmission- Downloaded：0: Audio signal input to the circuit, transmitter with infrared emission, the receiver to accept the AD processing, controlled by the sound of the amount of light, in addition to the temperature real time acquisition and di
Update : 2025-01-23 Size : 3.42mb Publisher : 崔兴
demo4 Downloaded：0: The AXI4-stream protocol, used to debug, test code, IPcore
Update : 2025-01-23 Size : 24kb Publisher : mingming
SUBWAY Downloaded：0: 1、Designing a valuation in line with the current standard of Wuhan Metro ticket vending machines。2、Each subway station setting a switch, set the $ 10 and one yuan two coin slot（Analog Switches），Set four digital tube, res
Update : 2025-01-23 Size : 2.39mb Publisher : 顾庆佳
gdi1 Downloaded：0: Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoder
Update : 2025-01-23 Size : 1kb Publisher : skb
QAM_verilog Downloaded：0: FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
Update : 2025-01-23 Size : 4kb Publisher : 饶黎
proyecto-I2C Downloaded：0: It s a VERILOG code to initiate a I2C protocol on an FPGA and an EEPROM of 512 KB
Update : 2025-01-23 Size : 132kb Publisher : yunta23
dds_cordic Downloaded：0: This is my own DDS based on series of the pipelined CORDIC algorithm， a frequency control word：32 bit .The number of CORDIC iterations for the 15 time。
Update : 2025-01-23 Size : 4.12mb Publisher : 陈杰
TLC1650 Downloaded：0: TLC1650driver Verilog HDL
Update : 2025-01-23 Size : 4.46mb Publisher : 李英豪
ML605_RX_H264 Downloaded：0: Solution of H.264 video compression hardware design language, based on FPGA language
Update : 2025-01-23 Size : 2kb Publisher : 呈祥
dianzhen Downloaded：0: After the dot-based FPGA module, input Chinese information can be progressive scan
Update : 2025-01-23 Size : 752kb Publisher :
dianyuan Downloaded：0: AD three buttons control channel to achieve power conversion
Update : 2025-01-23 Size : 468kb Publisher :

« 1 2 ... .63 .64 .65 .66 .67 568.69 .70 .71 .72 .73 ... 4311 »

Search in result