VHDL-FPGA-Verilog List Page 569

VHDL-FPGA-Verilog list

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ddfs Downloaded：0: IT IS THE CIRCUIT WHICH EXACTLY WORK AS SINE WAVE GENERATOR, THIS CAN BE EFFICIENTLY USED IN THE COMMUNICATIONS SYSTEMS
Update : 2025-01-23 Size : 87kb Publisher : ajay kumar
4-2-compressor Downloaded：0: IT IS THE HYBRID COMPRESSOR WHICH WILL BE USEFUL LOW POWER SINCE THE GATE COUNT AND DELAY REQUIRED IS VERY LESS COMPARED TO THE NORMAL DESIGN
Update : 2025-01-23 Size : 1.53mb Publisher : ajay kumar
vid_clkgen Downloaded：0: Xilinx xapp sink displayport vid clk geneator source
Update : 2025-01-23 Size : 1kb Publisher : asdfqqqwa
submicron-technology Downloaded：0: IT IS THE TECHNOLOGY TO REDUCE THE SHORT CIRCUIT LEKAGE POWER IN CMOS TECHNOLOGY. BY THIS WE CAN AVOID THE SHORT CIRCUIT POWER
Update : 2025-01-23 Size : 7kb Publisher : ajay kumar
image-rotation Downloaded：0: FPGA-based image processing system generator rotation, the use of image rotation system generator handler. This procedure is based on matlab run under the system generator.
Update : 2025-01-23 Size : 155kb Publisher : wyj
SRC Downloaded：0: an implementation of Pipelined CPU in verilog
Update : 2025-01-23 Size : 7kb Publisher : zyh
scan_led Downloaded：0: Each clock, counting time, achieve 8 scan display, turn on the digital tube display 13579BDF, can choose EDA experimental box, FPGA EP1C6Q240C8.
Update : 2025-01-23 Size : 1kb Publisher : LP
MB Downloaded：0: Digital stopwatch design based on VHDL, FPGA experimental platform under development
Update : 2025-01-23 Size : 217kb Publisher : 李耀
r7lite Downloaded：0: R7Lite is a PCIe Reference design based on Xilinx Kintex7 FPGA,including FPGA code ,Linux Driver and Testing A
Update : 2025-01-23 Size : 20.67mb Publisher : yao
m_serial Downloaded：0: m sequence generation. 3 300 m-order sequence cascade, resulting in an approximate number of random numbers. Output 32 of the random numbers and the parallel clock output comprises serial output.
Update : 2025-01-23 Size : 1kb Publisher : 汪海兵
CfgDDS_9910 Downloaded：0: dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done hands
Update : 2025-01-23 Size : 1kb Publisher : 汪海兵
cordic Downloaded：0: cordic code, suitable for beginners to learn and exchange
Update : 2025-01-23 Size : 1kb Publisher : 吕攀攀

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