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VHDL-FPGA-Verilog list
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FPGA-based Verilog language implementation of six decimal counter
Update : 2025-01-23 Size : 221kb Publisher :

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A serial port communication, realizing the development board and the transfer of data between computers
Update : 2025-01-23 Size : 1kb Publisher : 崔文超

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ADS1278 8-channel ADC data collection procedures, AD sampling depth of 24bit, 16bit output reserved. Write state machine.
Update : 2025-01-23 Size : 1kb Publisher : 郭俊媛

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Display driver works based EP3C16 of VGA. Clock 40M, pictures stored in the ROM of the FPGA, VGA display resolution is 800* 600* 60Hz, store pictures need 800* 600 (bit), due to EP3C16 the ROM is not big enough, ROM for
Update : 2025-01-23 Size : 10.73mb Publisher : 郭俊媛

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IDEA algorithm implementation
Update : 2025-01-23 Size : 2.98mb Publisher : 曹宇

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4 of C6201s through the HPI interface logic design of interconnection with CPLD, including the VHDL program
Update : 2025-01-23 Size : 3.69mb Publisher : 郭玉东

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VHDL language based digital clock, there are component instantiation, modify clock function Quartus II platform
Update : 2025-01-23 Size : 4.35mb Publisher : 尜尜

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Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file
Update : 2025-01-23 Size : 3.91mb Publisher : 杨玉

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a Table tennis game in spartran_3A
Update : 2025-01-23 Size : 9kb Publisher : 程伟

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a music play program in FPGA
Update : 2025-01-23 Size : 6kb Publisher : 程伟

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Spartan 3e basys2 Pin control file
Update : 2025-01-23 Size : 1kb Publisher : 李超惠

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Now for the SPI slave in the FPGA. Since the SPI bus is typically much slower than the FPGA operating clock speed, we choose to over-sample the SPI bus using the FPGA clock. That makes the slave code slightly more compli
Update : 2025-01-23 Size : 1kb Publisher : 齐宇心
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