VHDL-FPGA-Verilog List Page 570

VHDL-FPGA-Verilog list

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embed_xilinx Downloaded：0: xilinx sdk 3e
Update : 2025-01-23 Size : 9.58mb Publisher : 黄海岸
nios_EPCS_SDRAM Downloaded：0: DE2 FPGA NIOS 13.1
Update : 2025-01-23 Size : 23.35mb Publisher : 黄海岸
clock Downloaded：0: Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function
Update : 2025-01-23 Size : 13kb Publisher : Gareth
mol60 Downloaded：0: mold 60 counter
Update : 2025-01-23 Size : 485kb Publisher : 李九阳
SPWM Downloaded：2: Produce three-level SPWM by look-up table
Update : 2025-01-23 Size : 4.22mb Publisher : Jim
lut Downloaded：0: verilog lookup table functions to achieve the basic function lookup table can be used as reference for the preparation of a lookup table
Update : 2025-01-23 Size : 4.1mb Publisher : 李九阳
action_vip_uart Downloaded：0: FPGA UART
Update : 2025-01-23 Size : 808kb Publisher : tangping
fifo Downloaded：0: CAN bus, DSP+ FPGA+ SJA1000 architecture, FPGA logic is responsible for the design, FPGA is responsible in this document have dsp and sja1000 Communications
Update : 2025-01-23 Size : 4kb Publisher : 张浩阳
control_logic Downloaded：0: PCI bus state machine programs written using burst mode, single-cycle can be used, no burst mode driver, a very good thing, oh
Update : 2025-01-23 Size : 2kb Publisher : 张浩阳
uart_send Downloaded：0: Serial transmission program, verified by numerous equipment, reliable baud 2M, the system clock 40M
Update : 2025-01-23 Size : 1kb Publisher : 张浩阳
24bit-dadda-multiplier Downloaded：0: IT IS HIGHBRID MULTIPLIER WHERE WILL BE USEFUL TO GET HIGH SPEED MULTIPLICATION IN PROCESSORS
Update : 2025-01-23 Size : 8kb Publisher : ajay kumar
reversible-squarer Downloaded：0: it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates
Update : 2025-01-23 Size : 2kb Publisher : ajay kumar

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