VHDL-FPGA-Verilog List Page 589

VHDL-FPGA-Verilog list

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vga Downloaded：0: VGA with Verilog HDL code written, breadboard verified.
Update : 2025-01-24 Size : 2kb Publisher : Daniel
sram_test Downloaded：0: Written using Verilog SRAM test program, which Xianxiang SRAM write data, and then read out the data for comparison.
Update : 2025-01-24 Size : 1kb Publisher : Daniel
flash Downloaded：0: Written using Verilog FLASH test program. Xianxiang FLASH write data inside, and then read out the data for comparison.
Update : 2025-01-24 Size : 1kb Publisher : Daniel
IIR Downloaded：0: Achieve an IIR filter with Verilog and simulation in ISE inside.
Update : 2025-01-24 Size : 1kb Publisher : Daniel
SDRAM Downloaded：0: Written using Verilog SDRAM test program. Xianxiang SDRAM write data inside, and then read out the data for comparison.
Update : 2025-01-24 Size : 8kb Publisher : Daniel
advconfig Downloaded：0: In the Xilinx Zynq development board, ADV chip through the IIC configuration.
Update : 2025-01-24 Size : 105kb Publisher : ycfh1ss
DULE-RAM Downloaded：0: Based on dual port ram VERILOG example, the relatively simple, not very complicated, entry understand it.
Update : 2025-01-24 Size : 99kb Publisher : 张是非
project Downloaded：0: Nanjing subway station， based on the beginning and the end station, automatic calculation of fares.
Update : 2025-01-24 Size : 147kb Publisher : 王苏
clock18div Downloaded：0: Clock Divider, divfactor of 18
Update : 2025-01-24 Size : 1kb Publisher : Huy
Digital_Filter_FPGA Downloaded：0: Digital Filter in VHDL
Update : 2025-01-24 Size : 1kb Publisher : Huy
SR_SerIn Downloaded：0: Shift Register, Serial In Parallel Out VHDL
Update : 2025-01-24 Size : 1kb Publisher : Huy
Testbench_SR_SerIn Downloaded：0: Testbench for Shift Register, Serial in Parallel out
Update : 2025-01-24 Size : 7kb Publisher : Huy

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