VHDL-FPGA-Verilog List Page 592

VHDL-FPGA-Verilog list

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Verilog_HDL_elevator Downloaded：0: FPGA-based five-story elevator control logic implemented in Verilog design
Update : 2025-01-24 Size : 18kb Publisher : 柯家豪
AES Downloaded：0: AES hardware encryption and decryption algorithm description language, it is worth learning!
Update : 2025-01-24 Size : 12kb Publisher : zhangwei
Achievetrafficlights- Downloaded：0: Achieve traffic light simulation, a simple program to understand, it is suitable for novices and beginners
Update : 2025-01-24 Size : 50kb Publisher : 杨明
FPGA-based-hand-gesture-recognition-system Downloaded：0: FPGA based hand gesture recognition system
Update : 2025-01-24 Size : 687kb Publisher : ABHISHEK
DCT_Final Downloaded：0: 8 point approximate dct for image compression the purpose compression algorithm
Update : 2025-01-24 Size : 17.97mb Publisher : Maddy
small8 Downloaded：0: This a sample microprocessor with a bi-directional data bus and RAM in software created in VHDL run on a cyclone 3 FPGA.
Update : 2025-01-24 Size : 3.96mb Publisher : jeofner
4bit-microprocessor Downloaded：0: This file is 4bit microprocessor that included a variety of modules like ALU,Progrem Counter and ACC etc It is to calculate 4bit binary Topblock is top level module.
Update : 2025-01-24 Size : 2.46mb Publisher : chakyuseok
car Downloaded：0: Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors
Update : 2025-01-24 Size : 432kb Publisher : 郭广宇
EP2C5T144_VGA Downloaded：0: VGA EP2C5T altera QuartusII VHDL FPGA CPLD passed
Update : 2025-01-24 Size : 1.62mb Publisher : 寒雪亮
PEX8311_test Downloaded：1: PEX 8311 OK PCI e cycloneIII altera quartus FPGA CPLD
Update : 2025-01-24 Size : 1.09mb Publisher : 寒雪亮
TEXIO Downloaded：0: TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
Update : 2025-01-24 Size : 52kb Publisher : 寒雪亮
S1_38yima_NEW Downloaded：0: This experiment mainly to achieve a 3/8 decoder, in this experiment the procedure by SW1, SW2, SW3, respectively, corresponding to three binary. SW3 SW2 SW1: the corresponding figures and diode 0 0 0: 0 DD1 0 0 1: 1 DD2
Update : 2025-01-24 Size : 62kb Publisher : 赵厉

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