VHDL-FPGA-Verilog List Page 590

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .85 .86 .87 .88 .89 590.91 .92 .93 .94 .95 ... 4311 »

tuxingandvhdlsheji Downloaded：0: The FPGA development instance of graphic and VHDL mixed input circuit design. Note: please send files in directories below in English at compile time
Update : 2025-01-24 Size : 1.22mb Publisher : pld
7renbiaojueqi Downloaded：0: The FPGA development instance of the design with VHDL voter of seven people
Update : 2025-01-24 Size : 1.1mb Publisher : pld
duogongnengshuzizhong Downloaded：0: FPGA development instance of multi-function digital clock. The function of the multi-function digital clock should have are: show- points- second, hour, hour and minute basic function such as adjustable.
Update : 2025-01-24 Size : 1.52mb Publisher : pld
shuzimiaobiao Downloaded：0: FPGA development instance of digital stopwatch. 7 yards tube display. Stopwatch because its timing precision, high resolution (0.01 seconds), the income to the extensive application in various arena.
Update : 2025-01-24 Size : 1.53mb Publisher : pld
8wei7duanshumaguanxianshi Downloaded：0: The FPGA development instance of eight seven segment digital tube dynamic display circuit design.
Update : 2025-01-24 Size : 1.09mb Publisher : pld
IMAGE_ROTATION_v2 Downloaded：0: Implementing the rotation of image based on DE2-115 board. Used switch SW[2:0] to control the orientation of rotating image(±45°&±90°).
Update : 2025-01-24 Size : 293kb Publisher : QPHuang
sdram_src Downloaded：0: FPGA-based read and write control, sdram, easy to understand, verilog code Description
Update : 2025-01-24 Size : 10kb Publisher : 张红玉
big_data_encoder Downloaded：0: This paper introduces an FPGA-based controller design multi memory chip data acquisition board. The card through a line with ATA-6 standard IDE interface, using PIO mode data acquisition board and PC connectivity. FPGA c
Update : 2025-01-24 Size : 5.5mb Publisher : lvhenan
cmp42 Downloaded：0: Used for the design of multiplier, 8 Booth decoding multiplier, 4-2 compressed structure, accelerate the multiplication rate
Update : 2025-01-24 Size : 2.85mb Publisher : 成栋
e2prom_rd Downloaded：0: Operation is applied, the verilog code used in the E2PROM chips was introduced for I2C timing operation and store data
Update : 2025-01-24 Size : 10.84mb Publisher : 成栋
hex7segb Downloaded：0: Implimentation of the switches and 7 segment display bit counter on an Altera DE2 baord via VHDL code on the Cyclone II FPGA
Update : 2025-01-24 Size : 338kb Publisher : Casey
Lab10Part3 Downloaded：0: Quarturs environment Verilog documents. English characters display panel for displaying the seven standard LED. Oh, can not be used directly, remember to change the name of the corresponding module.
Update : 2025-01-24 Size : 1kb Publisher : 王强

« 1 2 ... .85 .86 .87 .88 .89 590.91 .92 .93 .94 .95 ... 4311 »

Search in result