VHDL-FPGA-Verilog List Page 600

VHDL-FPGA-Verilog list

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modulation-and-VHDL-program- Downloaded：0: Such information can help people learn the language learning how to program baseband modulation simulation.
Update : 2025-01-24 Size : 343kb Publisher : 桂婷
EDA-program Downloaded：0: This code can help people learn the language of learning how to write a program to realize the function of the computer.
Update : 2025-01-24 Size : 32kb Publisher : 桂婷
The-taxi-meter-program- Downloaded：0: 这个程序可以帮助学习这种语言的人学习如何编写程序实现出租车计价器的功能。
Update : 2025-01-24 Size : 112kb Publisher : 桂婷
Part-1-DWT-haar-using-VHDL Downloaded：0: VHDL language using haar wavelet transform transform.
Update : 2025-01-24 Size : 17kb Publisher : nancy
Part-2-DWT-haar-using-VHDL Downloaded：0: Using VHDL language haar wavelet transform other program transformation.
Update : 2025-01-24 Size : 16kb Publisher : nancy
spwm3 Downloaded：1: The time required to generate SPWM signals with dead by 0,1 sequence. By H-bridge circuit to control the current through the SPWM signal shape.
Update : 2025-01-24 Size : 3.72mb Publisher : typ
jiaotongzhishideng Downloaded：0: Based on VHDL design of traffic lights. Traffic lights to simulate the design.
Update : 2025-01-24 Size : 375kb Publisher : typ
CAN Downloaded：0: CAN protocol controller implemented in Verilog（contain testbench） & instruction of CAN protocol & datasheet and user manual of SJA1
Update : 2025-01-24 Size : 12.22mb Publisher : zhangsong
distrbtdarth Downloaded：0: FIR FILTER DESIGNING USING DISTRIBUTED ARITHMETIC ALGORITHM
Update : 2025-01-24 Size : 697kb Publisher : neha
firfilterverilog Downloaded：0: FIR FILTER DESIGNED IN VERILOG FOR 4 BIT MULTIPLIER
Update : 2025-01-24 Size : 140kb Publisher : neha
carrysaveadder Downloaded：0: carry save adder for addition of 8 bit inputs
Update : 2025-01-24 Size : 890kb Publisher : neha
factoredcsd Downloaded：0: FIR FILTER USING FCSD TECHNIQUE FOR REPRESENTING COEFFICIENT
Update : 2025-01-24 Size : 1.14mb Publisher : neha

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