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VHDL-FPGA-Verilog list
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ahb_master
Downloaded:0
AHB master system generator in verilog
Update
: 2025-01-24
Size
: 9kb
Publisher
:
Prashanth R
Array-multiplier
Downloaded:0
Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
Update
: 2025-01-24
Size
: 1kb
Publisher
:
Prashanth R
pid
Downloaded:0
pid controller design based vhdl code in xilinx code
Update
: 2025-01-24
Size
: 1kb
Publisher
:
GOPALAKRISHNAN E
WEIBOLU
Downloaded:0
the code based on ISE
Update
: 2025-01-24
Size
: 2.15mb
Publisher
:
姜蘅育
I2C
Downloaded:0
Lattice I2C VHDL source code
Update
: 2025-01-24
Size
: 2.86mb
Publisher
:
gary
piano_fina1
Downloaded:0
VHDL simple electronic organ based games, can realize the voice, dot matrix display, countdown, scoring function
Update
: 2025-01-24
Size
: 1011kb
Publisher
:
zhangxiangrui
router_five_port
Downloaded:0
On-chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs on output physical channels. Buffers, unfortunately, consume significant portions
Update
: 2025-01-24
Size
: 5kb
Publisher
:
Rosario Gowthaman
i2c-master
Downloaded:0
verilog IP for i2c master controller
Update
: 2025-01-24
Size
: 956kb
Publisher
:
guoqingsheng
DE2_SD_Card_Audio
Downloaded:0
This program is written in Verilog language, the main function is to read and play sdcard audio file
Update
: 2025-01-24
Size
: 3.93mb
Publisher
:
zucezuanyong
pwm_auto
Downloaded:0
PWM for VHDL program
Update
: 2025-01-24
Size
: 1kb
Publisher
:
khefin
memory_sizer_latest.tar
Downloaded:0
This logic module takes care of sizing bus transfers between a small microprocessor and its memory.It enables the microprocessor to generate access requests for different widths (read/write BYTE, WORD and D WORD, etc.) u
Update
: 2025-01-24
Size
: 262kb
Publisher
:
Prashanth R
TestProject
Downloaded:0
it use altera cyclone iii ep3c10e144 and cypress cy7c68013a to pc using nios dma to transmit data to pc via cy7c68013
Update
: 2025-01-24
Size
: 28.25mb
Publisher
:
梁定宇
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