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VHDL-FPGA-Verilog list
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7_07_DCMSim
Downloaded:0
xilinx demo code
Update
: 2025-01-24
Size
: 1.37mb
Publisher
:
钱学文
DIVIDER
Downloaded:0
verilog code for divider verilog code for dividerverilog code for divider
Update
: 2025-01-24
Size
: 2kb
Publisher
:
HP
nrf
Downloaded:0
nrf24l01 and fpga
Update
: 2025-01-24
Size
: 5.62mb
Publisher
:
王崎
shuzizhonganjian
Downloaded:0
Design a digital clock, this design requires a 12 or 24 hexadecimal hexadecimal have the hours, minutes, seconds, chronograph function digital clock, and can be adjusted hours and minutes.
Update
: 2025-01-24
Size
: 650kb
Publisher
:
bian
ma_slice_temp
Downloaded:0
verilog code temp h
Update
: 2025-01-24
Size
: 1kb
Publisher
:
Ethanhao
lab4
Downloaded:0
to realize keyboard funtion
Update
: 2025-01-24
Size
: 410kb
Publisher
:
wjt
meimei
Downloaded:0
Electronic clock that can display time, date, sports stopwatch, alarm
Update
: 2025-01-24
Size
: 2.12mb
Publisher
:
krist
final-project
Downloaded:0
final project- design processor
Update
: 2025-01-24
Size
: 2kb
Publisher
:
duyphan
Architecture-for-Dataflow-Graphs-with-Feedback.ra
Downloaded:0
Architecture for Dataflow Graphs with Feedback
Update
: 2025-01-24
Size
: 297kb
Publisher
:
duyphan
VHDL_-position-control
Downloaded:0
This program written in VHDL language of stepper motor positioning control program
Update
: 2025-01-24
Size
: 5kb
Publisher
:
王强
hdl-master
Downloaded:0
AD9361' s ip nuclear, debugging has been passed on vivado can run through. AD9361 is a dual-channel transceiver convenient, usually used in 3G/4G base stations.
Update
: 2025-01-24
Size
: 1.26mb
Publisher
:
liufei
LCD-control-VHDL-program
Downloaded:0
These programs can help people learn VHDL language better understanding of VHDL, and how to use the program to control the LED.
Update
: 2025-01-24
Size
: 10kb
Publisher
:
桂婷
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.96
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.99
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601
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4311
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