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VHDL-FPGA-Verilog list
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This a non-synchronous triggering of VHDL, click to clear the circuit and synchronization trigger, click to clear the circuit design
Update : 2025-01-31 Size : 2.13mb Publisher :

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This the music of IC design VHDL, designed by Max Plus II results will be displayed.
Update : 2025-01-31 Size : 396kb Publisher :

here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily
Update : 2025-01-31 Size : 147kb Publisher : eli

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this a example for ZYNQ 7
Update : 2025-01-31 Size : 1.3mb Publisher : 祝清瑞

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M25P40 flash
Update : 2025-01-31 Size : 2.4mb Publisher : 李俊

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A nice fpga receive ps2 keyboard program
Update : 2025-01-31 Size : 545kb Publisher : qi

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The latest generation C5 on altera development board DA, AD conversion data
Update : 2025-01-31 Size : 1.9mb Publisher : qi

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C5 on the latest generation of altera development board HDMI display information
Update : 2025-01-31 Size : 9.04mb Publisher : qi

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Quartus II realized by the respondent timer settings, roughly the time display function, countdown reminder, the pause button and so on.
Update : 2025-01-31 Size : 474kb Publisher : 边松林

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SOC AMBA bus interface code for understanding AHB APB protocol
Update : 2025-01-31 Size : 12.18mb Publisher : 舒洲

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this is a code of a 8-bit preocessor
Update : 2025-01-31 Size : 34kb Publisher : jimish

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I2S example is existing at that file
Update : 2025-01-31 Size : 25kb Publisher : fatih mercimek
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