VHDL-FPGA-Verilog List Page 662

VHDL-FPGA-Verilog list

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FPGA-VGA Downloaded：0: Based FPGA VGA basic source crystal display 640 x 480 resolution, 50M
Update : 2025-01-31 Size : 465kb Publisher : 2633063
SRTP2 Downloaded：0: Verilog HDL-based FPGA use encryption algorithms written 128bitAES circuit
Update : 2025-01-31 Size : 13.21mb Publisher : lshmenor
clock_retrive_lsy Downloaded：0: Using for E1 interface, support 2M frequency recovery and retime
Update : 2025-01-31 Size : 1kb Publisher : 李仕意
CPLD_EXample Downloaded：0: CPLD is very suitable for novices to learn the routines, the lit water lights, step by step advanced to VGA.
Update : 2025-01-31 Size : 6.19mb Publisher : 贾宁宁
project_wave_gen_code Downloaded：0: Design and implement a can produce sine, triangle, and sawtooth waveform generator. The operating frequency of 60MHz, can generate 1MHz, 2MHz, 3MHz, 4MHz, 5MHz, 6MHz, 10MHz sine, triangle, and sawtooth. The magnitude of
Update : 2025-01-31 Size : 1.07mb Publisher : 辛永超
lcd Downloaded：0: This code is written in verilog use drive LCD1602 Which LCD1602 display in English. (LCD with font)
Update : 2025-01-31 Size : 1kb Publisher : 刘天宇
ad6655_150 Downloaded：0: The program is controlled by FPGA AD6655, AD6655 register value is changed by the state machine, for control purposes, Found Available
Update : 2025-01-31 Size : 3.17mb Publisher : npudn99
regfor24 Downloaded：0: it s a clock for 24 hours .use verilogHDL to write the project ,it s easy to understand.
Update : 2025-01-31 Size : 3.48mb Publisher : 郭亚飞
e_piano Downloaded：0: I have written an electronic piano source, you can download and try, good use
Update : 2025-01-31 Size : 71kb Publisher : 郭亚飞
FIX_ONE_ROW_ROM Downloaded：0: This a text-based LCD display through matrix liquid crystal display with a state machine
Update : 2025-01-31 Size : 1kb Publisher :
Lab1~3 Downloaded：0: This a register of VHDL, Latch, tri-state box, count divider circuit and clock generator circuit
Update : 2025-01-31 Size : 2.12mb Publisher :
Lab4 Downloaded：0: This a synchronous clear circuit VHDL synchronize with non-clear analog circuits and circuit design of
Update : 2025-01-31 Size : 522kb Publisher :

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