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Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation, source code and so on. For learning reference, hope yo
Update : 2025-01-31 Size : 414kb Publisher : FEIFEI

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With CPLD control the audio output to realize the music playback function, timing control.
Update : 2025-01-31 Size : 295kb Publisher : 张永龙

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real matrix package is very goood
Update : 2025-01-31 Size : 265kb Publisher : savastakan

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some impurement of Vhdl libary (floating point vs..)
Update : 2025-01-31 Size : 114kb Publisher : savastakan

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VHDL extension, it is very good for this aim
Update : 2025-01-31 Size : 101kb Publisher : savastakan

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verilog tutorial it is very good tutorial
Update : 2025-01-31 Size : 352kb Publisher : savastakan

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it is very good tutorial about verilog
Update : 2025-01-31 Size : 450kb Publisher : savastakan

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it is very good tutorial, it is about vverilog
Update : 2025-01-31 Size : 752kb Publisher : savastakan

simple processor with wirting in vhdl
Update : 2025-01-31 Size : 357kb Publisher : savastakan

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When this experiment to design a display hours, minutes, seconds, digital clock, time on the seven-segment LED display, display numbers as a decimal number. By developing digital clock panel buttons to adjust the time, r
Update : 2025-01-31 Size : 2kb Publisher : 刘旭

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Designed with a fixed baud rate of UART serial port transceiver can achieve 9600 baud serial communication, able to communicate with the PC serial port, support for 8-bit data bits, 1 bit stop bit, no parity, no hardware
Update : 2025-01-31 Size : 3kb Publisher : 刘旭

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Frame synchronization state machine is mainly to overcome all kinds of unexpected situations that may occur in communications, including loss of signal, the communication channel error caused by the interruption, try to
Update : 2025-01-31 Size : 4kb Publisher : 刘旭
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