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VHDL-FPGA-Verilog list
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3 bits of arbitrary binary sequence detector,simulation with Quartus 10.0+ modelsim 6.5SE,report forms
Update : 2025-03-01 Size : 88kb Publisher : dailanfeng

Programmable filter design,simulation with Quartus 10.0+ modelsim 6.5SE , reports
Update : 2025-03-01 Size : 242kb Publisher : dailanfeng

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Digital frequency meter,simulation with Quartus 10.0+ modelsim 6.5SE ,reports。
Update : 2025-03-01 Size : 271kb Publisher : dailanfeng

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Counter display circuit,simulation with Quartus 10.0+ modelsim 6.5SE, reports
Update : 2025-03-01 Size : 240kb Publisher : dailanfeng

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Sequence Detector (1110010) designs, simulation with Quartus 10.0+ modelsim 6.5SE , reports
Update : 2025-03-01 Size : 160kb Publisher : dailanfeng

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Taximeter VHDL procedures, suitable for beginners.
Update : 2025-03-01 Size : 27kb Publisher : 石磊

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In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
Update : 2025-03-01 Size : 53kb Publisher : 喻国芳

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In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch
Update : 2025-03-01 Size : 2.95mb Publisher : 喻国芳

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Johnson counts
Update : 2025-03-01 Size : 228kb Publisher : 柳攸

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UART Receiver module
Update : 2025-03-01 Size : 2kb Publisher : tyb0220

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FPGA to emif
Update : 2025-03-01 Size : 5kb Publisher : tyb0220

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simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers
Update : 2025-03-01 Size : 5.31mb Publisher : octo
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