Description: Their use VHDL to write a serial program, debug the success of the project and used in the hope that beginners can learn from the next
- [uart_verilog] - include UART port of VERILOG source, the
- [serial_VHDL] - FPGA for serial communication procedure
- [Altera_uart_VHDL] - FPGA/CPLD applications, UART communicati
- [uart] - Serial communication protocol, you can b
- [uart_v11] - serial UART VHDL Language Program. I deb
- [EP1C3_12_5_RSV] - FPGA-based digital storage oscilloscope,
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