Welcome!
[Sign In]
!
[Sign Up]
!
Front-page it
|
Collect it
| [
中国-简体中文
]
CodeBus
codebus.net
Hot search:
Source
embeded
web
remote control
p2p
game
More...
FAQ
Fav
Home
SourceCode
Web Code
Develop Tools
Document
E-Books
Other Resource
Get Coins
Member
Location:
Downloads
Other resource
Title:
syn_frame
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
75.44kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
msy585
Description:
Frame Synchronization Verilog HDL source code to achieve synchronization receiver
Downloaders recently:
[
More information of uploader msy585
]
To Search:
receiver
frame verilog
store packet
[
very-good-ok-ref-ddr-sdram-verilog
] - Sdr SDRAM controller reference design, v
[
fpga_ofdm
] - This is the article
[
frequency_estimation
] - OFDM signals in frequency offset correct
[
FPGA_bit_clock_data_recovery
] - New FPGA-based data bit sync clock extra
[
bit-catchingupFPGA
] - This article is in the FPGA, the realiza
[
SDHAnalysis
] - SDH fiber-optic communication data frame
[
Verilogdezhentongbu
] - Verilog language-based digital communica
[
Discrete_Time_Queue
] - Discrete Time Queue write a program to p
[
syn_frame
] - verilog-based frame synchronization sear
[
Descrambler
] - phase detection in ofdm Verilog program,
File list
(Check if you may need any files):
Main Category
SourceCode
Web Code
Develop Tools
Document
Other resource
Category
Games
Plug-in
Trojan
Program registrar
SDK
Other
About site
Total codes:
120
M
Total size:
1500
GB
Today updated:368
Members:1688565
Today members:634
Total members:198568
Downloaded:1200M
Sign UP
Help
Support
What's CodeBus
SiteMap
Contact us
CodeBus www.codebus.net
“CodeBus” is the largest source code store in internet!
1999-2018
CodeBus
All Rights Reserved.