Description: Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report
To Search:
- [clock] - VHDL based on the digital clock has an a
- [clock_design] - Digital Clock in Verilog code, quartusII
- [N!] - Using assembly language written by the f
- [vhdl_design] - Design a complete digital electronic clo
- [shuzizhong2008] - This paper describes the design of digit
- [eda] - Curriculum design to design and FPGA imp
- [clk_vhdl] - Quartus II project files, is a typical F
- [shuzizhong] - Verilog digital clock can be written in
- [clock] - Using Verilog HDL language multi-functio
- [szz] - Digital clock written in Verilog, the us
File list (Check if you may need any files):
EDA课程设计（带完整设计报告）
.............................\EDA课程设计报告.doc
.............................\陈屹-数字钟
.............................\...........\.untf
.............................\...........\a.ANT
.............................\...........\a.fdo
.............................\...........\a.tbw
.............................\...........\a.udo
.............................\...........\a.vhw
.............................\...........\alarm1.cmd_log
.............................\...........\alarm1.lso
.............................\...........\alarm1.ngc
.............................\...........\alarm1.ngr
.............................\...........\alarm1.prj
.............................\...........\alarm1.stx
.............................\...........\alarm1.syr
.............................\...........\alm.vhdl
.............................\...........\automake.log
.............................\...........\b.ANT
.............................\...........\b.fdo
.............................\...........\b.tbw
.............................\...........\b.tdo
.............................\...........\b.timesim_vhw
.............................\...........\b.udo
.............................\...........\b.vhw
.............................\...........\bitgen.ut
.............................\...........\c.ANT
.............................\...........\c.fdo
.............................\...........\c.jhd
.............................\...........\c.tbw
.............................\...........\c.udo
.............................\...........\c.vhw
.............................\...........\cc.ANT
.............................\...........\cc.fdo
.............................\...........\cc.tbw
.............................\...........\cc.tdo
.............................\...........\cc.timesim_vhw
.............................\...........\cc.udo
.............................\...........\cc.vhw
.............................\...........\coregen.log
.............................\...........\coregen.prj
.............................\...........\dd.ANT
.............................\...........\dd.fdo
.............................\...........\dd.tbw
.............................\...........\dd.udo
.............................\...........\dd.vhw
.............................\...........\e.ANT
.............................\...........\e.fdo
.............................\...........\e.tbw
.............................\...........\e.udo
.............................\...........\e.vhw
.............................\...........\fenping.cmd_log
.............................\...........\fenping.lso
.............................\...........\fenping.prj
.............................\...........\fenping.syr
.............................\...........\fenping.vhdl
.............................\...........\fenping_vhdl.prj
.............................\...........\hour.vhdl
.............................\...........\hour1.bld
.............................\...........\hour1.cmd_log
.............................\...........\hour1.lso
.............................\...........\hour1.mrp
.............................\...........\hour1.nc1
.............................\...........\hour1.ncd
.............................\...........\hour1.ngc
.............................\...........\hour1.ngd
.............................\...........\hour1.ngm
.............................\...........\hour1.ngr
.............................\...........\hour1.pad
.............................\...........\hour1.pad_txt
.............................\...........\hour1.par
.............................\...........\hour1.par_nlf
.............................\...........\hour1.pcf
.............................\...........\hour1.placed_ncd_tracker
.............................\...........\hour1.prj
.............................\...........\hour1.routed_ncd_tracker
.............................\...........\hour1.spl
.............................\...........\hour1.stx
.............................\...........\hour1.sym
.............................\...........\hour1.syr
.....
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