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VHDL-FPGA-Verilog
Title:
decode
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Category:
VHDL-FPGA-Verilog
Tags:
[PDF]
File Size:
231kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
zh19861109
Description:
VHDL language based on the cycle of the program code encoder to a (15,6) cyclic code as an example
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File list
(Check if you may need any files):
decode ......\decode.txt ......\循环码编译码方法研究.pdf
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