Description: The design is a sequence detector, can detect a long series of 11 signals, according to the needs may be appropriate to expand its sequence length
- [xuliejiance] - Sequence Detector absolutely good for ED
- [xljcq] - Using VHDL language sequence detector de
- [chk] - This procedure implements a sequence det
- [pwm-c] - VHDL prepared using PWM control procedur
- [jishuqi] - This article counters 11 Experimental re
- [seg_test] - VHDL-based sequence detector design
- [code] - The use of state machines to design a se
- [Sequencedetector] - Sequence detector (for example 1010111)
File list (Check if you may need any files):
JIANCHE
.......\CHK
.......\...\CHK.asm.rpt
.......\...\CHK.done
.......\...\CHK.fit.rpt
.......\...\CHK.fit.summary
.......\...\CHK.flow.rpt
.......\...\CHK.map.rpt
.......\...\CHK.map.summary
.......\...\CHK.pin
.......\...\CHK.pof
.......\...\CHK.qpf
.......\...\CHK.qsf
.......\...\CHK.qws
.......\...\CHK.sim.rpt
.......\...\CHK.sof
.......\...\CHK.tan.rpt
.......\...\CHK.tan.summary
.......\...\CHK.vhd
.......\...\CHK.vwf
.......\...\db
.......\...\..\CHK.asm.qmsg
.......\...\..\CHK.cbx.xml
.......\...\..\CHK.cmp.cdb
.......\...\..\CHK.cmp.hdb
.......\...\..\CHK.cmp.logdb
.......\...\..\CHK.cmp.rdb
.......\...\..\CHK.cmp.tdb
.......\...\..\CHK.cmp0.ddb
.......\...\..\CHK.dbp
.......\...\..\CHK.db_info
.......\...\..\CHK.eco.cdb
.......\...\..\CHK.eds_overflow
.......\...\..\CHK.fit.qmsg
.......\...\..\CHK.hier_info
.......\...\..\CHK.hif
.......\...\..\CHK.map.cdb
.......\...\..\CHK.map.hdb
.......\...\..\CHK.map.logdb
.......\...\..\CHK.map.qmsg
.......\...\..\CHK.pre_map.cdb
.......\...\..\CHK.pre_map.hdb
.......\...\..\CHK.psp
.......\...\..\CHK.pss
.......\...\..\CHK.rtlv.hdb
.......\...\..\CHK.rtlv_sg.cdb
.......\...\..\CHK.rtlv_sg_swap.cdb
.......\...\..\CHK.sgdiff.cdb
.......\...\..\CHK.sgdiff.hdb
.......\...\..\CHK.sim.cvwf
.......\...\..\CHK.sim.hdb
.......\...\..\CHK.sim.qmsg
.......\...\..\CHK.sim.rdb
.......\...\..\CHK.sld_design_entry.sci
.......\...\..\CHK.sld_design_entry_dsc.sci
.......\...\..\CHK.smp_dump.txt
.......\...\..\CHK.syn_hier_info
.......\...\..\CHK.tan.qmsg
.......\...\..\prev_cmp_CHK.asm.qmsg
.......\...\..\prev_cmp_CHK.fit.qmsg
.......\...\..\prev_cmp_CHK.map.qmsg
.......\...\..\prev_cmp_CHK.sim.qmsg
.......\...\..\prev_cmp_CHK.tan.qmsg
.......\...\..\wed.wsf
.......\...\prev_cmp_CHK.qmsg
.......\JIANCHE
.......\.......\CHK.vhd
.......\.......\db
.......\.......\..\JIANCHE.asm.qmsg
.......\.......\..\JIANCHE.cbx.xml
.......\.......\..\JIANCHE.cmp.cdb
.......\.......\..\JIANCHE.cmp.hdb
.......\.......\..\JIANCHE.cmp.logdb
.......\.......\..\JIANCHE.cmp.rdb
.......\.......\..\JIANCHE.cmp.tdb
.......\.......\..\JIANCHE.cmp0.ddb
.......\.......\..\JIANCHE.dbp
.......\.......\..\JIANCHE.db_info
.......\.......\..\JIANCHE.eco.cdb
.......\.......\..\JIANCHE.eds_overflow
.......\.......\..\JIANCHE.fit.qmsg
.......\.......\..\JIANCHE.hier_info
.......\.......\..\JIANCHE.hif
.......\.......\..\JIANCHE.map.cdb
.......\.......\..\JIANCHE.map.hdb
.......\.......\..\JIANCHE.map.logdb
.......\.......\..\JIANCHE.map.qmsg
.......\.......\..\JIANCHE.pre_map.cdb
.......\.......\..\JIANCHE.pre_map.hdb
.......\.......\..\JIANCHE.psp
.......\.......\..\JIANCHE.pss
.......\.......\..\JIANCHE.rpp.qmsg
.......\.......\..\JIANCHE.rtlv.hdb
.......\.......\..\JIANCHE.rtlv_sg.cdb
.......\.......\..\JIANCHE.rtlv_sg_swap.cdb
.......\.......\..\JIANCHE.sgate.rvd
.......\.......\..\JIANCHE.sgate_sm.rvd
.......\.......\..\JIANCHE.sgdiff.cdb
.......\.......\..\JIANCHE.sgdiff.hdb
.......\.......\..\JIANCHE.sim.cvwf
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