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Title: seg_test Download
 Description: VHDL-based sequence detector design
 Downloaders recently: [More information of uploader 84875466]
  • [FIFO] - Asynchronous FIFO controller Verilog Des
  • [xljcq] - Using VHDL language sequence detector de
  • [detect] - A sequence detector design. Procedure is
  • [sequence_inspector] - Sequence detector can be used to detect
  • [JIANCHE] - The design is a sequence detector, can d
  • [dds] - Using VHDL hardware description language
  • [multi] - Based on CPLD/FPGA multiplier of 16 to a
  • [seqdet] - On the serial input data streams to dete
  • [fpga_USB2] - FPGA-based on the realization of USB2.0
  • [EP1C3_81_SCHK] - Sequence detector design there is a comp
File list (Check if you may need any files):
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..........\db
..........\..\prev_cmp_seg_check.asm.qmsg
..........\..\prev_cmp_seg_check.fit.qmsg
..........\..\prev_cmp_seg_check.map.qmsg
..........\..\prev_cmp_seg_check.qmsg
..........\..\prev_cmp_seg_check.sim.qmsg
..........\..\prev_cmp_seg_check.tan.qmsg
..........\..\seg_check.asm.qmsg
..........\..\seg_check.asm_labs.ddb
..........\..\seg_check.cbx.xml
..........\..\seg_check.cmp.cdb
..........\..\seg_check.cmp.hdb
..........\..\seg_check.cmp.logdb
..........\..\seg_check.cmp.rdb
..........\..\seg_check.cmp.tdb
..........\..\seg_check.cmp0.ddb
..........\..\seg_check.db_info
..........\..\seg_check.eco.cdb
..........\..\seg_check.eds_overflow
..........\..\seg_check.fit.qmsg
..........\..\seg_check.fnsim.cdb
..........\..\seg_check.fnsim.hdb
..........\..\seg_check.fnsim.qmsg
..........\..\seg_check.hier_info
..........\..\seg_check.hif
..........\..\seg_check.map.cdb
..........\..\seg_check.map.hdb
..........\..\seg_check.map.logdb
..........\..\seg_check.map.qmsg
..........\..\seg_check.pre_map.cdb
..........\..\seg_check.pre_map.hdb
..........\..\seg_check.rtlv.hdb
..........\..\seg_check.rtlv_sg.cdb
..........\..\seg_check.rtlv_sg_swap.cdb
..........\..\seg_check.sgdiff.cdb
..........\..\seg_check.sgdiff.hdb
..........\..\seg_check.signalprobe.cdb
..........\..\seg_check.sim.cvwf
..........\..\seg_check.sim.hdb
..........\..\seg_check.sim.qmsg
..........\..\seg_check.sim.rdb
..........\..\seg_check.simfam
..........\..\seg_check.sld_design_entry.sci
..........\..\seg_check.sld_design_entry_dsc.sci
..........\..\seg_check.smp_dump.txt
..........\..\seg_check.syn_hier_info
..........\..\seg_check.tan.qmsg
..........\..\seg_check.tis_db_list.ddb
..........\..\seg_check.tmw_info
..........\..\wed.wsf
..........\seg_check.asm.rpt
..........\seg_check.done
..........\seg_check.fit.rpt
..........\seg_check.fit.smsg
..........\seg_check.fit.summary
..........\seg_check.flow.rpt
..........\seg_check.map.rpt
..........\seg_check.map.summary
..........\seg_check.pin
..........\seg_check.pof
..........\seg_check.qpf
..........\seg_check.qsf
..........\seg_check.qws
..........\seg_check.sim.rpt
..........\seg_check.tan.rpt
..........\seg_check.tan.summary
..........\seg_check.vhd
..........\seg_check.vhd.bak
..........\seg_check.vwf
..........\seg_check2.vwf
..........\seg_check3.vwf
..........\seg_check4.vwf
..........\seg_check5.vwf
    

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