T3_USB_OUT CY7C68013 to send an external data, sen

Title: T3_USB_OUT

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Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
856kb
Update:
2012-11-26
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Uploaded by:
419256570

Description: CY7C68013 to send an external data, sent to the fpga, fpga examples of procedures

Downloaders recently: [More information of uploader 419256570]

To Search: cy7c68013 cy7c68013 fpga fpga cy7c68013 cy7c68013 vhdl T3_USB_OUT vhdl fpga usb T3_USB_OUT

[CY7c68013_FPGA_Read_Sram] - Reading SRAM in the FPGA, then pass on a
[CY7C68013_FX2] - cypress fx2 firmware code samples
[123963854732] - OV7620 detailed information for people l
[CycloneIII_SB_3C25] - Altera
[usbin_v1.7] - For the CY7C68013 and FPGA communication
[USB2_0] - CY7C68013 and FPGA controller USB2_0 int
[GPIORAM] - Infineon Single-chip development board e
[68013_SlaveFIFO] - cy7c68013 slave fifo mode code ,written
[usb] - In the high-speed data acquisition or tr
[SLAVE_FIFO_16BITS] - communication between 68013 and FPGA inc

File list (Check if you may need any files):

T3_USB_OUT
..........\Doc
..........\...\RCII-CY1C12开发板USB OUT示例说明.doc
..........\Firmware
..........\........\USB_OUT2.hex
..........\Proj
..........\....\cmp_state.ini
..........\....\db
..........\....\..\altsyncram_do82.tdf
..........\....\..\altsyncram_th92.tdf
..........\....\..\cntr_bv7.tdf
..........\....\..\cntr_dn7.tdf
..........\....\..\cntr_e29.tdf
..........\....\..\cntr_mo8.tdf
..........\....\..\cntr_nt9.tdf
..........\....\..\decode_9ie.tdf
..........\....\..\pc2fpga.asm.qmsg
..........\....\..\pc2fpga.cbx.xml
..........\....\..\pc2fpga.cmp.cdb
..........\....\..\pc2fpga.cmp.hdb
..........\....\..\pc2fpga.cmp.rdb
..........\....\..\pc2fpga.cmp.tdb
..........\....\..\pc2fpga.cmp0.ddb
..........\....\..\pc2fpga.db_info
..........\....\..\pc2fpga.eco.cdb
..........\....\..\pc2fpga.fit.qmsg
..........\....\..\pc2fpga.hier_info
..........\....\..\pc2fpga.hif
..........\....\..\pc2fpga.map.cdb
..........\....\..\pc2fpga.map.hdb
..........\....\..\pc2fpga.map.qmsg
..........\....\..\pc2fpga.pre_map.cdb
..........\....\..\pc2fpga.pre_map.hdb
..........\....\..\pc2fpga.psp
..........\....\..\pc2fpga.rtlv.hdb
..........\....\..\pc2fpga.rtlv_sg.cdb
..........\....\..\pc2fpga.rtlv_sg_swap.cdb
..........\....\..\pc2fpga.sgdiff.cdb
..........\....\..\pc2fpga.sgdiff.hdb
..........\....\..\pc2fpga.signalprobe.cdb
..........\....\..\pc2fpga.sld_design_entry.sci
..........\....\..\pc2fpga.sld_design_entry_dsc.sci
..........\....\..\pc2fpga.syn_hier_info
..........\....\..\pc2fpga.tan.qmsg
..........\....\..\pc2fpga_cmp.qrpt
..........\....\..\USB_OUT.smp_dump.txt
..........\....\pc2fpga.asm.rpt
..........\....\pc2fpga.cdf
..........\....\pc2fpga.done
..........\....\pc2fpga.fit.eqn
..........\....\pc2fpga.fit.rpt
..........\....\pc2fpga.fit.summary
..........\....\pc2fpga.flow.rpt
..........\....\pc2fpga.map.eqn
..........\....\pc2fpga.map.rpt
..........\....\pc2fpga.map.summary
..........\....\pc2fpga.pin
..........\....\pc2fpga.pof
..........\....\pc2fpga.qsf
..........\....\pc2fpga.sof
..........\....\pc2fpga.stp
..........\....\pc2fpga.tan.rpt
..........\....\pc2fpga.tan.summary
..........\....\pc2fpga_assignment_defaults.qdf
..........\....\USB_OUT.qpf
..........\....\USB_OUT.qws
..........\Src
..........\...\pc2fpga.v

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