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VHDL-FPGA-Verilog
Title:
usbin_v1.7
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
Description:
For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
Downloaders recently:
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More information of uploader
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To Search:
cy7c68013 fpga vhdl
CY7C68013 VHDL
cy7c68013 fpga
fpga fifo
CY7C68013 fifo
cy7c68013
[
usb2.0 principle and project develop
] - code of usb 2.0 develop, hope to help.
[
USBvc
] - vc prepared with the USB interface progr
[
USB-shujucaiji
] - USB Data Acquisition System papers-their
[
testApp
] - CY7C68013 chip USB2.0 speed test, VC-end
[
USB_daqu
] - Translation of foreign domestic
[
VHDL
] - High-quality VHDL code deal with ping-po
[
T3_USB_OUT
] - CY7C68013 to send an external data, sent
[
USB2_0
] - CY7C68013 and FPGA controller USB2_0 int
[
USB_kz
] - Cy7C68013 USB chip to provide the develo
[
interleaver
] - Veriog interwoven matrix of the realizat
File list
(Check if you may need any files):
usbin_v1.7.v
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