Description: Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
- [szzsybk] - VHDL design of a simple digital clock, t
- [digtalclk] - Using Altera s QuartusII procedures for
- [shuzizhong] - EDA system is based on a 24-hour digital
- [elc_clock] - Realize a display hours, minutes, second
- [shuzizhong] - The design of a can be hours, minutes, s
- [Digital_freq_tester] - VHDL figures prepared frequency tester,
- [EDAshuzhizhong] - The design of a can be hours, minutes, s
File list (Check if you may need any files):
rtl
...\clock.v
...\counter.v
...\display.v
...\temp_time.v
...\timer.v
...\transcript
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