DDR_SDRAM_controller ddr sdram realization of VHDL

Title: DDR_SDRAM_controller

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VHDL-FPGA-Verilog
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Update:
2012-11-26
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szyflyinsky

Description: ddr sdram realization of VHDL, including the realization of each module as well as the simulation file

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To Search: ddr ddr sdram sdram VHDL DDR VHDL SDRAM ddr controll vhdl

[bios-img] - BIOS source code, according to this sour
[ddr_sdram_controller_vhdl] - ddr_sdram controller vhdl code, which ad
[DDR_SDRAM_use_in_embedded] - many embedded systems, especially for im
[bujindianjiVHDL] - positioning stepper motor control system
[DDRSDRAM] - DDR sdram contains complete source code,
[DDR2_sdram] - DDR2 controller, it is by the compiler-g
[DDR_SDRAM_DesignSummarize] - Based on the Xilinx Spartan family of de
[DPRAM] - VHDL prepared to use dual-port Ram proce
[DDR_SDRAM_verilog] - DDR (double rate) SDRAM controller refer
[SDRAM] - SDRAM controller, Verilog coding, allows

File list (Check if you may need any files):

doc
...\ddr_sdram.pdf
help.txt
model
.....\mt46v4m16.vhd
.....\mti_pkg.vhd
PCB资源网.txt
route
.....\ddr_sdram.csf
.....\ddr_sdram.esf
.....\ddr_sdram.quartus
.....\ddr_sdram.vqm
.....\pll1.vhd
simulation
..........\APEX20KE_MF.VHD
..........\ddr_command.vhd
..........\ddr_control_interface.vhd
..........\ddr_data_path.vhd
..........\ddr_sdram.vhd
..........\ddr_sdram_tb.vhd
..........\io_utils.vhd
..........\lpm_pack.vhd
..........\modelsim.ini
..........\mt46v4m16.vhd
..........\mti_pkg.bak
..........\mti_pkg.vhd
..........\pll1.vhd
..........\readme.txt
..........\stdlogar.vhd
..........\util1164.vhd
..........\wave.do
..........\work
..........\....\altcam
..........\....\......\behave.dat
..........\....\......\behave.psm
..........\....\......\_primary.dat
..........\....\altclklock
..........\....\..........\behavior.dat
..........\....\..........\behavior.psm
..........\....\..........\_primary.dat
..........\....\altlvds_rx
..........\....\..........\behavior.dat
..........\....\..........\behavior.psm
..........\....\..........\_primary.dat
..........\....\altlvds_tx
..........\....\..........\behavior.dat
..........\....\..........\behavior.psm
..........\....\..........\_primary.dat
..........\....\command
..........\....\.......\rtl.dat
..........\....\.......\rtl.psm
..........\....\.......\_primary.dat
..........\....\control_interface
..........\....\.................\rtl.dat
..........\....\.................\rtl.psm
..........\....\.................\_primary.dat
..........\....\ddr_command
..........\....\...........\rtl.dat
..........\....\...........\rtl.psm
..........\....\...........\_primary.dat
..........\....\ddr_control_interface
..........\....\.....................\rtl.dat
..........\....\.....................\rtl.psm
..........\....\.....................\_primary.dat
..........\....\ddr_data_path
..........\....\.............\rtl.dat
..........\....\.............\rtl.psm
..........\....\.............\_primary.dat
..........\....\ddr_sdram
..........\....\.........\rtl.dat
..........\....\.........\rtl.psm
..........\....\.........\_primary.dat
..........\....\ddr_sdram_tb
..........\....\............\rtl.dat
..........\....\............\rtl.psm
..........\....\............\_primary.dat
..........\....\io_utils
..........\....\........\body.dat
..........\....\........\body.psm
..........\....\........\_primary.dat
..........\....\........\_vhdl.psm
..........\....\lpm_components
..........\....\..............\body.dat
..........\....\..............\body.psm
..........\....\..............\_primary.dat
..........\....\..............\_vhdl.psm
..........\....\mt46v4m16
..........\....\.........\behave.dat
..........\....\.........\behave.psm
..........\....\.........\_primary.dat
..........\....\mti_pkg
..........\....\.......\body.dat
..........\....\.......\body.psm
..........\....\.......\_primary.dat
..........\....\.......\_vhdl.psm
..........\....\pll1
..........\....\....\syn.dat
..........\....\....\syn.psm
..........\....\....\_primary.dat
..........\....\std_logic_arith

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