Description: SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
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SDRAM资料
.........\datasheets
.........\..........\42S83200B-16160B.pdf
.........\..........\SDRAM的原理和时序[1].pdf
.........\notes
.........\.....\ARM学习笔记.docx
.........\.....\SDRAM学习笔记.docx
.........\SDRAM控制器的verilog代码，含test_bench
.........\......................................\Sdram_ctrl
.........\......................................\..........\MT48LC16M16A2.v
.........\......................................\..........\Sdram_ctrl.cr.mti
.........\......................................\..........\Sdram_ctrl.mpf
.........\......................................\..........\Sdram_ctrl.v
.........\......................................\..........\Sdram_ctrl.vo
.........\......................................\..........\Sdram_ctrl_modelsim.xrf
.........\......................................\..........\Sdram_ctrl_v.sdo
.........\......................................\..........\top.v
.........\......................................\..........\transcript
.........\......................................\..........\vsim.wlf
.........\......................................\..........\work
.........\......................................\..........\....\@m@t48@l@c16@m16@a2
.........\......................................\..........\....\...................\verilog.asm
.........\......................................\..........\....\...................\_primary.dat
.........\......................................\..........\....\...................\_primary.vhd
.........\......................................\..........\....\@sdram_ctrl
.........\......................................\..........\....\...........\verilog.asm
.........\......................................\..........\....\...........\_primary.dat
.........\......................................\..........\....\...........\_primary.vhd
.........\......................................\..........\....\top
.........\......................................\..........\....\...\verilog.asm
.........\......................................\..........\....\...\_primary.dat
.........\......................................\..........\....\...\_primary.vhd
.........\......................................\..........\....\_info
.........\simulation model
.........\................\mt48lc16m16a2.v
.........\some links
.........\..........\SDRAM的寻址与预充电功能分析总结.mht
.........\..........\SDRAM的寻址知识及重要的参数.mht
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