File list (Check if you may need any files):
rtl
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\verilog
...\.......\CVS
...\.......\...\Entries
...\.......\...\Repository
...\.......\...\Root
...\.......\i2c_master_bit_ctrl.v
...\.......\i2c_master_byte_ctrl.v
...\.......\i2c_master_defines.v
...\.......\i2c_master_top.v
...\.......\timescale.v
...\vhdl
...\....\CVS
...\....\...\Entries
...\....\...\Repository
...\....\...\Root
...\....\I2C.VHD
...\....\i2c_master_bit_ctrl.vhd
...\....\i2c_master_byte_ctrl.vhd
...\....\i2c_master_top.vhd
...\....\readme
...\....\tst_ds1621.vhd
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